Search

My Trang Ton

Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1378040 [patent_doc_number] => 06566934 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-20 [patent_title] => 'Charge cancellation circuit for switched capacitor applications' [patent_app_type] => B1 [patent_app_number] => 10/029980 [patent_app_country] => US [patent_app_date] => 2001-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5089 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566934.pdf [firstpage_image] =>[orig_patent_app_number] => 10029980 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029980
Charge cancellation circuit for switched capacitor applications Dec 30, 2001 Issued
Array ( [id] => 6733778 [patent_doc_number] => 20030011413 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-16 [patent_title] => 'Low latency clock distribution' [patent_app_type] => new [patent_app_number] => 10/040750 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5682 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0011/20030011413.pdf [firstpage_image] =>[orig_patent_app_number] => 10040750 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/040750
Low latency clock distribution Dec 27, 2001 Issued
Array ( [id] => 1421563 [patent_doc_number] => 06525581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Duty correction circuit and a method of correcting a duty' [patent_app_type] => B1 [patent_app_number] => 10/033989 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3882 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525581.pdf [firstpage_image] =>[orig_patent_app_number] => 10033989 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033989
Duty correction circuit and a method of correcting a duty Dec 27, 2001 Issued
Array ( [id] => 1394915 [patent_doc_number] => 06552587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-22 [patent_title] => 'Synchronous semiconductor device for adjusting phase offset in a delay locked loop' [patent_app_type] => B2 [patent_app_number] => 10/033004 [patent_app_country] => US [patent_app_date] => 2001-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4268 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552587.pdf [firstpage_image] =>[orig_patent_app_number] => 10033004 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/033004
Synchronous semiconductor device for adjusting phase offset in a delay locked loop Dec 27, 2001 Issued
Array ( [id] => 1424181 [patent_doc_number] => 06518807 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Mixed delay locked loop circuit' [patent_app_type] => B1 [patent_app_number] => 10/026463 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2173 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518807.pdf [firstpage_image] =>[orig_patent_app_number] => 10026463 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026463
Mixed delay locked loop circuit Dec 26, 2001 Issued
Array ( [id] => 6681317 [patent_doc_number] => 20030117181 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-26 [patent_title] => 'HIGH ACCURACY METHOD FOR DETERMINING THE FREQUENCY OF A PULSE INPUT SIGNAL OVER A WIDE FREQUENCY RANGE' [patent_app_type] => new [patent_app_number] => 10/026228 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6501 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20030117181.pdf [firstpage_image] =>[orig_patent_app_number] => 10026228 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/026228
High accuracy method for determining the frequency of a pulse input signal over a wide frequency range Dec 20, 2001 Issued
Array ( [id] => 1419609 [patent_doc_number] => 06529055 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Method for adjusting the center frequency of a phase locked loop' [patent_app_type] => B1 [patent_app_number] => 10/024241 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2678 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529055.pdf [firstpage_image] =>[orig_patent_app_number] => 10024241 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/024241
Method for adjusting the center frequency of a phase locked loop Dec 20, 2001 Issued
Array ( [id] => 6527120 [patent_doc_number] => 20020109537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Phase-locked loop for reducing frequency lock time' [patent_app_type] => new [patent_app_number] => 10/034891 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20020109537.pdf [firstpage_image] =>[orig_patent_app_number] => 10034891 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034891
Phase-locked loop for reducing frequency lock time Dec 19, 2001 Issued
Array ( [id] => 1399279 [patent_doc_number] => 06549043 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Sample and hold circuit with compression and expansion' [patent_app_type] => B2 [patent_app_number] => 10/024755 [patent_app_country] => US [patent_app_date] => 2001-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1696 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549043.pdf [firstpage_image] =>[orig_patent_app_number] => 10024755 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/024755
Sample and hold circuit with compression and expansion Dec 19, 2001 Issued
Array ( [id] => 1407051 [patent_doc_number] => 06531905 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Flip-flop with metastability reduction' [patent_app_type] => B1 [patent_app_number] => 10/024816 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531905.pdf [firstpage_image] =>[orig_patent_app_number] => 10024816 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/024816
Flip-flop with metastability reduction Dec 18, 2001 Issued
Array ( [id] => 1349066 [patent_doc_number] => 06586971 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Adapting VLSI clocking to short term voltage transients' [patent_app_type] => B1 [patent_app_number] => 10/020114 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2068 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/586/06586971.pdf [firstpage_image] =>[orig_patent_app_number] => 10020114 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020114
Adapting VLSI clocking to short term voltage transients Dec 17, 2001 Issued
Array ( [id] => 6667063 [patent_doc_number] => 20030112046 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'PRECISE AND PROGRAMMABLE DUTY CYCLE GENERATOR' [patent_app_type] => new [patent_app_number] => 10/020528 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4635 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20030112046.pdf [firstpage_image] =>[orig_patent_app_number] => 10020528 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/020528
Precise and programmable duty cycle generator Dec 13, 2001 Issued
Array ( [id] => 1423050 [patent_doc_number] => 06509771 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Enhanced operational frequency for a precise and programmable duty cycle generator' [patent_app_type] => B1 [patent_app_number] => 10/017071 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3045 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509771.pdf [firstpage_image] =>[orig_patent_app_number] => 10017071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017071
Enhanced operational frequency for a precise and programmable duty cycle generator Dec 13, 2001 Issued
Array ( [id] => 1329422 [patent_doc_number] => 06603339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-05 [patent_title] => 'Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator' [patent_app_type] => B2 [patent_app_number] => 10/017744 [patent_app_country] => US [patent_app_date] => 2001-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 13 [patent_no_of_words] => 5689 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/603/06603339.pdf [firstpage_image] =>[orig_patent_app_number] => 10017744 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/017744
Precision aligned multiple concurrent duty cycles from a programmable duty cycle generator Dec 13, 2001 Issued
Array ( [id] => 7630834 [patent_doc_number] => 06636098 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Differential integrator and related circuitry' [patent_app_type] => B1 [patent_app_number] => 10/002007 [patent_app_country] => US [patent_app_date] => 2001-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 12444 [patent_no_of_claims] => 56 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636098.pdf [firstpage_image] =>[orig_patent_app_number] => 10002007 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/002007
Differential integrator and related circuitry Dec 4, 2001 Issued
Array ( [id] => 1422992 [patent_doc_number] => 06509764 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-21 [patent_title] => 'Low component circuit for reducing power dissipation capacitance' [patent_app_type] => B2 [patent_app_number] => 10/005640 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3062 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509764.pdf [firstpage_image] =>[orig_patent_app_number] => 10005640 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005640
Low component circuit for reducing power dissipation capacitance Dec 3, 2001 Issued
Array ( [id] => 1241662 [patent_doc_number] => 06683485 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Double translation voltage level shifter and method' [patent_app_type] => B1 [patent_app_number] => 10/004747 [patent_app_country] => US [patent_app_date] => 2001-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4473 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/683/06683485.pdf [firstpage_image] =>[orig_patent_app_number] => 10004747 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/004747
Double translation voltage level shifter and method Dec 3, 2001 Issued
Array ( [id] => 1591802 [patent_doc_number] => 06483367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-19 [patent_title] => 'Circuit arrangement for generating and amplifying an amplitude limited DC signal' [patent_app_type] => B2 [patent_app_number] => 10/011970 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3296 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483367.pdf [firstpage_image] =>[orig_patent_app_number] => 10011970 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/011970
Circuit arrangement for generating and amplifying an amplitude limited DC signal Dec 2, 2001 Issued
Array ( [id] => 6578246 [patent_doc_number] => 20020084810 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Method for outputting data and circuit configuration with driver circuit' [patent_app_type] => new [patent_app_number] => 10/005944 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8569 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084810.pdf [firstpage_image] =>[orig_patent_app_number] => 10005944 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/005944
Method for outputting data and circuit configuration with driver circuit Dec 2, 2001 Issued
Array ( [id] => 1422059 [patent_doc_number] => 06512399 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Offset-free rail-to-rail derandomizing peak detect-and-hold circuit' [patent_app_type] => B1 [patent_app_number] => 09/999237 [patent_app_country] => US [patent_app_date] => 2001-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2602 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/512/06512399.pdf [firstpage_image] =>[orig_patent_app_number] => 09999237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/999237
Offset-free rail-to-rail derandomizing peak detect-and-hold circuit Dec 2, 2001 Issued
Menu