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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6397250 [patent_doc_number] => 20020036531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'LATCH AND D-TYPE FLIP-FLOP' [patent_app_type] => new [patent_app_number] => 09/960522 [patent_app_country] => US [patent_app_date] => 2001-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10210 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0036/20020036531.pdf [firstpage_image] =>[orig_patent_app_number] => 09960522 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/960522
Latch and D-type flip-flop Sep 23, 2001 Issued
Array ( [id] => 1342248 [patent_doc_number] => 06593799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Circuit including forward body bias from supply voltage and ground nodes' [patent_app_type] => B2 [patent_app_number] => 09/957996 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9646 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593799.pdf [firstpage_image] =>[orig_patent_app_number] => 09957996 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957996
Circuit including forward body bias from supply voltage and ground nodes Sep 20, 2001 Issued
Array ( [id] => 1419637 [patent_doc_number] => 06529058 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-04 [patent_title] => 'Apparatus and method for obtaining stable delays for clock signals' [patent_app_type] => B2 [patent_app_number] => 09/956978 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 2304 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529058.pdf [firstpage_image] =>[orig_patent_app_number] => 09956978 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/956978
Apparatus and method for obtaining stable delays for clock signals Sep 20, 2001 Issued
Array ( [id] => 1535094 [patent_doc_number] => 06411143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Lock detector for a dual phase locked loop system' [patent_app_type] => B1 [patent_app_number] => 09/957201 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5499 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/411/06411143.pdf [firstpage_image] =>[orig_patent_app_number] => 09957201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957201
Lock detector for a dual phase locked loop system Sep 18, 2001 Issued
Array ( [id] => 7629207 [patent_doc_number] => 06819150 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method and apparatus for quick clock swapping using much slower asynchronous clock for power savings' [patent_app_type] => B1 [patent_app_number] => 09/957144 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2496 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 8 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/819/06819150.pdf [firstpage_image] =>[orig_patent_app_number] => 09957144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/957144
Method and apparatus for quick clock swapping using much slower asynchronous clock for power savings Sep 18, 2001 Issued
Array ( [id] => 7645058 [patent_doc_number] => 06472915 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method for charge pump tri-state and power down/up sequence without disturbing the output filter' [patent_app_type] => B1 [patent_app_number] => 09/955865 [patent_app_country] => US [patent_app_date] => 2001-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3370 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472915.pdf [firstpage_image] =>[orig_patent_app_number] => 09955865 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/955865
Method for charge pump tri-state and power down/up sequence without disturbing the output filter Sep 18, 2001 Issued
Array ( [id] => 7645053 [patent_doc_number] => 06472920 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'High speed latch circuit' [patent_app_type] => B1 [patent_app_number] => 09/953779 [patent_app_country] => US [patent_app_date] => 2001-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3833 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472920.pdf [firstpage_image] =>[orig_patent_app_number] => 09953779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/953779
High speed latch circuit Sep 16, 2001 Issued
Array ( [id] => 1583661 [patent_doc_number] => 06424190 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Apparatus and method for delay matching of full and divided clock signals' [patent_app_type] => B1 [patent_app_number] => 09/950572 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4405 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424190.pdf [firstpage_image] =>[orig_patent_app_number] => 09950572 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950572
Apparatus and method for delay matching of full and divided clock signals Sep 12, 2001 Issued
Array ( [id] => 1562543 [patent_doc_number] => 06437615 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Loop filter and method for generating a control signal in phase-locked loop circuits' [patent_app_type] => B1 [patent_app_number] => 09/951252 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5113 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437615.pdf [firstpage_image] =>[orig_patent_app_number] => 09951252 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951252
Loop filter and method for generating a control signal in phase-locked loop circuits Sep 12, 2001 Issued
Array ( [id] => 1399423 [patent_doc_number] => 06549050 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Programmable latch that avoids a non-desired output state' [patent_app_type] => B1 [patent_app_number] => 09/951369 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4662 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/549/06549050.pdf [firstpage_image] =>[orig_patent_app_number] => 09951369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951369
Programmable latch that avoids a non-desired output state Sep 12, 2001 Issued
Array ( [id] => 1407135 [patent_doc_number] => 06531910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-11 [patent_title] => 'Symmetric multiplexer' [patent_app_type] => B1 [patent_app_number] => 09/951008 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3182 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531910.pdf [firstpage_image] =>[orig_patent_app_number] => 09951008 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951008
Symmetric multiplexer Sep 11, 2001 Issued
Array ( [id] => 1598472 [patent_doc_number] => 06492855 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Flip flop which has complementary, symmetric, minimal timing skew outputs' [patent_app_type] => B1 [patent_app_number] => 09/950207 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4927 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492855.pdf [firstpage_image] =>[orig_patent_app_number] => 09950207 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950207
Flip flop which has complementary, symmetric, minimal timing skew outputs Sep 9, 2001 Issued
Array ( [id] => 1537050 [patent_doc_number] => 06489816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Frequency converter with direct current suppression' [patent_app_type] => B1 [patent_app_number] => 09/948514 [patent_app_country] => US [patent_app_date] => 2001-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3137 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/489/06489816.pdf [firstpage_image] =>[orig_patent_app_number] => 09948514 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948514
Frequency converter with direct current suppression Sep 6, 2001 Issued
Array ( [id] => 1421459 [patent_doc_number] => 06525574 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Gate bootstrapped CMOS sample-and-hold circuit' [patent_app_type] => B1 [patent_app_number] => 09/947989 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1998 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/525/06525574.pdf [firstpage_image] =>[orig_patent_app_number] => 09947989 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947989
Gate bootstrapped CMOS sample-and-hold circuit Sep 5, 2001 Issued
Array ( [id] => 1581011 [patent_doc_number] => 06448835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'High-speed leaf splitter for clock gating' [patent_app_type] => B1 [patent_app_number] => 09/947602 [patent_app_country] => US [patent_app_date] => 2001-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3807 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448835.pdf [firstpage_image] =>[orig_patent_app_number] => 09947602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947602
High-speed leaf splitter for clock gating Sep 5, 2001 Issued
Array ( [id] => 1553807 [patent_doc_number] => 06400201 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'Delay circuit and ring oscillator incorporating the same' [patent_app_type] => B1 [patent_app_number] => 09/945654 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 13276 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400201.pdf [firstpage_image] =>[orig_patent_app_number] => 09945654 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/945654
Delay circuit and ring oscillator incorporating the same Sep 4, 2001 Issued
Array ( [id] => 1603413 [patent_doc_number] => 06433595 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of system circuit design and circuitry for high speed data communication' [patent_app_type] => B1 [patent_app_number] => 09/947643 [patent_app_country] => US [patent_app_date] => 2001-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 20 [patent_no_of_words] => 5670 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433595.pdf [firstpage_image] =>[orig_patent_app_number] => 09947643 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/947643
Method of system circuit design and circuitry for high speed data communication Sep 4, 2001 Issued
Array ( [id] => 1345751 [patent_doc_number] => 06590427 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Phase frequency detector circuit having reduced dead band' [patent_app_type] => B2 [patent_app_number] => 09/946324 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4811 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/590/06590427.pdf [firstpage_image] =>[orig_patent_app_number] => 09946324 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/946324
Phase frequency detector circuit having reduced dead band Sep 3, 2001 Issued
Array ( [id] => 5871759 [patent_doc_number] => 20020047739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Modified clock signal generator' [patent_app_type] => new [patent_app_number] => 09/944388 [patent_app_country] => US [patent_app_date] => 2001-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3361 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20020047739.pdf [firstpage_image] =>[orig_patent_app_number] => 09944388 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/944388
Modified clock signal generator Sep 3, 2001 Abandoned
Array ( [id] => 1460334 [patent_doc_number] => 06426660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Duty-cycle correction circuit' [patent_app_type] => B1 [patent_app_number] => 09/943665 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2439 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426660.pdf [firstpage_image] =>[orig_patent_app_number] => 09943665 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943665
Duty-cycle correction circuit Aug 29, 2001 Issued
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