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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6060933 [patent_doc_number] => 20020030519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-14 [patent_title] => 'Phase locked loop having DC bias circuitry' [patent_app_type] => new [patent_app_number] => 09/943590 [patent_app_country] => US [patent_app_date] => 2001-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3487 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20020030519.pdf [firstpage_image] =>[orig_patent_app_number] => 09943590 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943590
Phase locked loop having DC bias circuitry Aug 29, 2001 Issued
Array ( [id] => 6430454 [patent_doc_number] => 20020175719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Transistor drive circuits and methods using selective discharge of terminal capacitance' [patent_app_type] => new [patent_app_number] => 09/942394 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3819 [patent_no_of_claims] => 58 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175719.pdf [firstpage_image] =>[orig_patent_app_number] => 09942394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942394
Transistor drive circuits and methods using selective discharge of terminal capacitance Aug 28, 2001 Abandoned
Array ( [id] => 6748440 [patent_doc_number] => 20030042960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-06 [patent_title] => 'Variable delay circuit and method, and delay locked loop, memory device and computer system using same' [patent_app_type] => new [patent_app_number] => 09/943779 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5682 [patent_no_of_claims] => 77 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20030042960.pdf [firstpage_image] =>[orig_patent_app_number] => 09943779 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/943779
Variable delay circuit and method, and delay locked loop, memory device and computer system using same Aug 28, 2001 Issued
Array ( [id] => 1354305 [patent_doc_number] => 06580321 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Active clamping circuit for power amplifiers' [patent_app_type] => B1 [patent_app_number] => 09/939183 [patent_app_country] => US [patent_app_date] => 2001-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2111 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580321.pdf [firstpage_image] =>[orig_patent_app_number] => 09939183 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/939183
Active clamping circuit for power amplifiers Aug 23, 2001 Issued
Array ( [id] => 1419844 [patent_doc_number] => 06529077 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Gain compensation circuit for CMOS amplifiers' [patent_app_type] => B1 [patent_app_number] => 09/933964 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6102 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/529/06529077.pdf [firstpage_image] =>[orig_patent_app_number] => 09933964 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/933964
Gain compensation circuit for CMOS amplifiers Aug 21, 2001 Issued
Array ( [id] => 1028752 [patent_doc_number] => 06882197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Method for generating an output clock-pulse and a corresponding clock-pulse generation circuit' [patent_app_type] => utility [patent_app_number] => 10/362514 [patent_app_country] => US [patent_app_date] => 2001-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2174 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882197.pdf [firstpage_image] =>[orig_patent_app_number] => 10362514 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/362514
Method for generating an output clock-pulse and a corresponding clock-pulse generation circuit Aug 21, 2001 Issued
Array ( [id] => 6238434 [patent_doc_number] => 20020044016 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Matching apparatus' [patent_app_type] => new [patent_app_number] => 09/934403 [patent_app_country] => US [patent_app_date] => 2001-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4382 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20020044016.pdf [firstpage_image] =>[orig_patent_app_number] => 09934403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/934403
Matching apparatus Aug 20, 2001 Issued
Array ( [id] => 1387987 [patent_doc_number] => 06559716 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-06 [patent_title] => 'Switchable operational amplifier for switched op-amp applications' [patent_app_type] => B2 [patent_app_number] => 09/932892 [patent_app_country] => US [patent_app_date] => 2001-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4382 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559716.pdf [firstpage_image] =>[orig_patent_app_number] => 09932892 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932892
Switchable operational amplifier for switched op-amp applications Aug 19, 2001 Issued
Array ( [id] => 1425787 [patent_doc_number] => 06507233 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Method and circuit for compensating VT induced drift in monolithic logarithmic amplifier' [patent_app_type] => B1 [patent_app_number] => 09/920220 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 5149 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507233.pdf [firstpage_image] =>[orig_patent_app_number] => 09920220 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/920220
Method and circuit for compensating VT induced drift in monolithic logarithmic amplifier Aug 1, 2001 Issued
Array ( [id] => 6743978 [patent_doc_number] => 20030021161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'SENSE AMPLIFIER THRESHOLD COMPENSATION' [patent_app_type] => new [patent_app_number] => 09/917059 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3561 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0021/20030021161.pdf [firstpage_image] =>[orig_patent_app_number] => 09917059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/917059
Sense amplifier threshold compensation Jul 26, 2001 Issued
Array ( [id] => 7639596 [patent_doc_number] => 06396320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-05-28 [patent_title] => 'Clock control method and circuit' [patent_app_type] => B2 [patent_app_number] => 09/915541 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 13778 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 7 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396320.pdf [firstpage_image] =>[orig_patent_app_number] => 09915541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915541
Clock control method and circuit Jul 26, 2001 Issued
Array ( [id] => 7077230 [patent_doc_number] => 20010040474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Clock control method and circuit' [patent_app_type] => new [patent_app_number] => 09/915542 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 13885 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 28 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040474.pdf [firstpage_image] =>[orig_patent_app_number] => 09915542 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915542
Clock control method and circuit Jul 26, 2001 Issued
Array ( [id] => 1429897 [patent_doc_number] => 06504414 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-01-07 [patent_title] => 'Clock control method and circuit' [patent_app_type] => B2 [patent_app_number] => 09/915283 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 13764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/504/06504414.pdf [firstpage_image] =>[orig_patent_app_number] => 09915283 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915283
Clock control method and circuit Jul 26, 2001 Issued
Array ( [id] => 1519565 [patent_doc_number] => 06501316 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Clock control method and circuit' [patent_app_type] => B2 [patent_app_number] => 09/915556 [patent_app_country] => US [patent_app_date] => 2001-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 13780 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/501/06501316.pdf [firstpage_image] =>[orig_patent_app_number] => 09915556 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/915556
Clock control method and circuit Jul 26, 2001 Issued
Array ( [id] => 1382940 [patent_doc_number] => 06563355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Recovery circuit generating low jitter reproduction clock' [patent_app_type] => B2 [patent_app_number] => 09/897931 [patent_app_country] => US [patent_app_date] => 2001-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 29 [patent_no_of_words] => 19639 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/563/06563355.pdf [firstpage_image] =>[orig_patent_app_number] => 09897931 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/897931
Recovery circuit generating low jitter reproduction clock Jul 4, 2001 Issued
Array ( [id] => 6430563 [patent_doc_number] => 20020175732 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Active auto zero circuit for programmable time continuous open loop amplifiers' [patent_app_type] => new [patent_app_number] => 09/896279 [patent_app_country] => US [patent_app_date] => 2001-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5011 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20020175732.pdf [firstpage_image] =>[orig_patent_app_number] => 09896279 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/896279
Active auto zero circuit for programmable time continuous open loop amplifiers Jun 28, 2001 Issued
Array ( [id] => 1142285 [patent_doc_number] => 06781428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Input circuit with switched reference signals' [patent_app_type] => B2 [patent_app_number] => 09/894188 [patent_app_country] => US [patent_app_date] => 2001-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4794 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/781/06781428.pdf [firstpage_image] =>[orig_patent_app_number] => 09894188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/894188
Input circuit with switched reference signals Jun 26, 2001 Issued
Array ( [id] => 1597907 [patent_doc_number] => 06384662 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Electronic circuit' [patent_app_type] => B1 [patent_app_number] => 09/786268 [patent_app_country] => US [patent_app_date] => 2001-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1463 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384662.pdf [firstpage_image] =>[orig_patent_app_number] => 09786268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/786268
Electronic circuit Jun 12, 2001 Issued
Array ( [id] => 1597824 [patent_doc_number] => 06384641 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Signal sampling circuit with high frequency noise immunity and method therefor' [patent_app_type] => B1 [patent_app_number] => 09/873818 [patent_app_country] => US [patent_app_date] => 2001-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2861 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384641.pdf [firstpage_image] =>[orig_patent_app_number] => 09873818 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/873818
Signal sampling circuit with high frequency noise immunity and method therefor Jun 3, 2001 Issued
Array ( [id] => 1462143 [patent_doc_number] => 06392446 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Device and method for reducing a time constant of a data bus during a voltage transition' [patent_app_type] => B1 [patent_app_number] => 09/872296 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6321 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392446.pdf [firstpage_image] =>[orig_patent_app_number] => 09872296 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/872296
Device and method for reducing a time constant of a data bus during a voltage transition May 31, 2001 Issued
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