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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1562577 [patent_doc_number] => 06437624 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-20 [patent_title] => 'Edge-triggered latch with symmetric complementary pass-transistor logic data path' [patent_app_type] => B1 [patent_app_number] => 09/810027 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4081 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437624.pdf [firstpage_image] =>[orig_patent_app_number] => 09810027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810027
Edge-triggered latch with symmetric complementary pass-transistor logic data path Mar 14, 2001 Issued
Array ( [id] => 1469127 [patent_doc_number] => 06459332 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-01 [patent_title] => 'Digitally-operated analog buffer amplifiers' [patent_app_type] => B2 [patent_app_number] => 09/803752 [patent_app_country] => US [patent_app_date] => 2001-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2462 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/459/06459332.pdf [firstpage_image] =>[orig_patent_app_number] => 09803752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803752
Digitally-operated analog buffer amplifiers Mar 11, 2001 Issued
Array ( [id] => 6920776 [patent_doc_number] => 20010028261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-10-11 [patent_title] => 'Driver circuit' [patent_app_type] => new [patent_app_number] => 09/801062 [patent_app_country] => US [patent_app_date] => 2001-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4461 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0028/20010028261.pdf [firstpage_image] =>[orig_patent_app_number] => 09801062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/801062
Differential transmission driver circuit Mar 7, 2001 Issued
Array ( [id] => 4378728 [patent_doc_number] => 06288577 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Active fail-safe detect circuit for differential receiver' [patent_app_type] => 1 [patent_app_number] => 9/681237 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2650 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288577.pdf [firstpage_image] =>[orig_patent_app_number] => 681237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681237
Active fail-safe detect circuit for differential receiver Mar 1, 2001 Issued
Array ( [id] => 1502871 [patent_doc_number] => 06486721 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Latch control circuit for crossing clock domains' [patent_app_type] => B2 [patent_app_number] => 09/798662 [patent_app_country] => US [patent_app_date] => 2001-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3925 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486721.pdf [firstpage_image] =>[orig_patent_app_number] => 09798662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/798662
Latch control circuit for crossing clock domains Mar 1, 2001 Issued
Array ( [id] => 1487374 [patent_doc_number] => 06366137 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-04-02 [patent_title] => 'Very low-power comparison device' [patent_app_type] => B2 [patent_app_number] => 09/795055 [patent_app_country] => US [patent_app_date] => 2001-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4098 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366137.pdf [firstpage_image] =>[orig_patent_app_number] => 09795055 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/795055
Very low-power comparison device Feb 25, 2001 Issued
Array ( [id] => 7643329 [patent_doc_number] => 06429713 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'D-FF circuit' [patent_app_type] => B2 [patent_app_number] => 09/790672 [patent_app_country] => US [patent_app_date] => 2001-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 6396 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429713.pdf [firstpage_image] =>[orig_patent_app_number] => 09790672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/790672
D-FF circuit Feb 22, 2001 Issued
Array ( [id] => 1492274 [patent_doc_number] => 06417708 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Resistively-loaded current-mode output buffer with slew rate control' [patent_app_type] => B1 [patent_app_number] => 09/782842 [patent_app_country] => US [patent_app_date] => 2001-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4242 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417708.pdf [firstpage_image] =>[orig_patent_app_number] => 09782842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782842
Resistively-loaded current-mode output buffer with slew rate control Feb 13, 2001 Issued
Array ( [id] => 1342044 [patent_doc_number] => 06593783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-15 [patent_title] => 'Compensation circuit for fractional-N frequency PLL synthesizer' [patent_app_type] => B2 [patent_app_number] => 09/776510 [patent_app_country] => US [patent_app_date] => 2001-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 7208 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593783.pdf [firstpage_image] =>[orig_patent_app_number] => 09776510 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/776510
Compensation circuit for fractional-N frequency PLL synthesizer Feb 1, 2001 Issued
Array ( [id] => 6891400 [patent_doc_number] => 20010017562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-30 [patent_title] => 'Flip-flop circuit' [patent_app_type] => new [patent_app_number] => 09/771642 [patent_app_country] => US [patent_app_date] => 2001-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3370 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0017/20010017562.pdf [firstpage_image] =>[orig_patent_app_number] => 09771642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/771642
Flip-flop circuit Jan 29, 2001 Issued
Array ( [id] => 6743333 [patent_doc_number] => 20030020516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Voltage comparator circuit and substrate bias adjusting circuit using same' [patent_app_type] => new [patent_app_number] => 09/769306 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4710 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20030020516.pdf [firstpage_image] =>[orig_patent_app_number] => 09769306 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/769306
Voltage comparator circuit and substrate bias adjusting circuit using same Jan 25, 2001 Issued
Array ( [id] => 7077228 [patent_doc_number] => 20010040472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Method and circuitry for supplying clock to internal circuit' [patent_app_type] => new [patent_app_number] => 09/768238 [patent_app_country] => US [patent_app_date] => 2001-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7024 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040472.pdf [firstpage_image] =>[orig_patent_app_number] => 09768238 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/768238
Method and circuitry for supplying clock to internal circuit Jan 24, 2001 Issued
Array ( [id] => 1553791 [patent_doc_number] => 06400197 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-06-04 [patent_title] => 'Delay device having a delay lock loop and method of calibration thereof' [patent_app_type] => B2 [patent_app_number] => 09/766952 [patent_app_country] => US [patent_app_date] => 2001-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 4152 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/400/06400197.pdf [firstpage_image] =>[orig_patent_app_number] => 09766952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/766952
Delay device having a delay lock loop and method of calibration thereof Jan 21, 2001 Issued
Array ( [id] => 4415091 [patent_doc_number] => 06310504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Data transmission circuit for compensating difference of speed' [patent_app_type] => 1 [patent_app_number] => 9/765517 [patent_app_country] => US [patent_app_date] => 2001-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2659 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310504.pdf [firstpage_image] =>[orig_patent_app_number] => 765517 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765517
Data transmission circuit for compensating difference of speed Jan 18, 2001 Issued
Array ( [id] => 4312323 [patent_doc_number] => 06326825 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Accurate time delay system and method utilizing an inaccurate oscillator' [patent_app_type] => 1 [patent_app_number] => 9/765188 [patent_app_country] => US [patent_app_date] => 2001-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3674 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326825.pdf [firstpage_image] =>[orig_patent_app_number] => 765188 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/765188
Accurate time delay system and method utilizing an inaccurate oscillator Jan 17, 2001 Issued
Array ( [id] => 6902043 [patent_doc_number] => 20010000952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-10 [patent_title] => 'Clock control method and circuit' [patent_app_type] => new-utility [patent_app_number] => 09/755152 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 52 [patent_no_of_words] => 13966 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 27 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000952.pdf [firstpage_image] =>[orig_patent_app_number] => 09755152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755152
Clock control method and circuit Jan 7, 2001 Issued
Array ( [id] => 1551333 [patent_doc_number] => 06346838 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Internal offset-canceled phase locked loop-based deskew buffer' [patent_app_type] => B1 [patent_app_number] => 09/755849 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3233 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346838.pdf [firstpage_image] =>[orig_patent_app_number] => 09755849 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/755849
Internal offset-canceled phase locked loop-based deskew buffer Jan 4, 2001 Issued
Array ( [id] => 4378791 [patent_doc_number] => 06288581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Low-voltage differential-signalling output buffer with pre-emphasis' [patent_app_type] => 1 [patent_app_number] => 9/681101 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 3687 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288581.pdf [firstpage_image] =>[orig_patent_app_number] => 681101 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/681101
Low-voltage differential-signalling output buffer with pre-emphasis Jan 4, 2001 Issued
Array ( [id] => 6881858 [patent_doc_number] => 20010048330 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-06 [patent_title] => 'Clock generator and digital or telephone poratble terminal using the same' [patent_app_type] => new [patent_app_number] => 09/750797 [patent_app_country] => US [patent_app_date] => 2001-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3224 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20010048330.pdf [firstpage_image] =>[orig_patent_app_number] => 09750797 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750797
Clock generator and digital or telephone portable terminal using the same Jan 1, 2001 Issued
Array ( [id] => 4312404 [patent_doc_number] => 06326830 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Automatic clock calibration circuit' [patent_app_type] => 1 [patent_app_number] => 9/750145 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2146 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326830.pdf [firstpage_image] =>[orig_patent_app_number] => 750145 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/750145
Automatic clock calibration circuit Dec 28, 2000 Issued
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