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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1545048 [patent_doc_number] => 06373333 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Vital AND gate apparatus and method' [patent_app_type] => B1 [patent_app_number] => 09/752107 [patent_app_country] => US [patent_app_date] => 2000-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3331 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373333.pdf [firstpage_image] =>[orig_patent_app_number] => 09752107 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/752107
Vital AND gate apparatus and method Dec 28, 2000 Issued
Array ( [id] => 4387775 [patent_doc_number] => 06304119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Timing generating apparatus with self-calibrating capability' [patent_app_type] => 1 [patent_app_number] => 9/748926 [patent_app_country] => US [patent_app_date] => 2000-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 2296 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304119.pdf [firstpage_image] =>[orig_patent_app_number] => 748926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748926
Timing generating apparatus with self-calibrating capability Dec 26, 2000 Issued
Array ( [id] => 7643341 [patent_doc_number] => 06429701 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-06 [patent_title] => 'Drive circuit for semiconductor power device and semiconductor switching circuit using the drive circuit' [patent_app_type] => B2 [patent_app_number] => 09/745735 [patent_app_country] => US [patent_app_date] => 2000-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 18 [patent_no_of_words] => 13339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 6 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429701.pdf [firstpage_image] =>[orig_patent_app_number] => 09745735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/745735
Drive circuit for semiconductor power device and semiconductor switching circuit using the drive circuit Dec 25, 2000 Issued
Array ( [id] => 7643343 [patent_doc_number] => 06429699 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Generator of neuron transfer function and its derivative' [patent_app_type] => B1 [patent_app_number] => 09/741447 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1927 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/429/06429699.pdf [firstpage_image] =>[orig_patent_app_number] => 09741447 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/741447
Generator of neuron transfer function and its derivative Dec 18, 2000 Issued
Array ( [id] => 6947257 [patent_doc_number] => 20010020889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-13 [patent_title] => 'Antifuse programming circuit' [patent_app_type] => new [patent_app_number] => 09/739294 [patent_app_country] => US [patent_app_date] => 2000-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1288 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0020/20010020889.pdf [firstpage_image] =>[orig_patent_app_number] => 09739294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739294
Antifuse programming circuit Dec 18, 2000 Issued
Array ( [id] => 7630848 [patent_doc_number] => 06636084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-10-21 [patent_title] => 'Sample and hold circuit' [patent_app_type] => B2 [patent_app_number] => 09/739189 [patent_app_country] => US [patent_app_date] => 2000-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2900 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 13 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636084.pdf [firstpage_image] =>[orig_patent_app_number] => 09739189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/739189
Sample and hold circuit Dec 17, 2000 Issued
Array ( [id] => 1562615 [patent_doc_number] => 06437633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-08-20 [patent_title] => 'Switching element, stage and system' [patent_app_type] => B2 [patent_app_number] => 09/733420 [patent_app_country] => US [patent_app_date] => 2000-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5694 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/437/06437633.pdf [firstpage_image] =>[orig_patent_app_number] => 09733420 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733420
Switching element, stage and system Dec 7, 2000 Issued
Array ( [id] => 1413405 [patent_doc_number] => 06535033 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-18 [patent_title] => 'Peak hold circuit' [patent_app_type] => B2 [patent_app_number] => 09/733180 [patent_app_country] => US [patent_app_date] => 2000-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2496 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/535/06535033.pdf [firstpage_image] =>[orig_patent_app_number] => 09733180 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/733180
Peak hold circuit Dec 6, 2000 Issued
Array ( [id] => 7105056 [patent_doc_number] => 20010004323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-21 [patent_title] => 'Switching arrangements' [patent_app_type] => new-utility [patent_app_number] => 09/725160 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1588 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20010004323.pdf [firstpage_image] =>[orig_patent_app_number] => 09725160 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725160
Switching arrangements Nov 28, 2000 Issued
Array ( [id] => 7063919 [patent_doc_number] => 20010043204 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'Display device capable of collecting substantially all power charged to capacitive load in display panel' [patent_app_type] => new [patent_app_number] => 09/725245 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5518 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20010043204.pdf [firstpage_image] =>[orig_patent_app_number] => 09725245 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/725245
Display device capable of collecting substantially all power charged to capacitive load in display panel Nov 28, 2000 Issued
Array ( [id] => 1548224 [patent_doc_number] => 06445220 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Method and apparatus for fully-differential half-circulator for bi-directional small-signal signaling' [patent_app_type] => B1 [patent_app_number] => 09/717465 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3504 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445220.pdf [firstpage_image] =>[orig_patent_app_number] => 09717465 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/717465
Method and apparatus for fully-differential half-circulator for bi-directional small-signal signaling Nov 19, 2000 Issued
09/623105 INTEGRATED CIRCUIT HAVING A SUPPLY VOLTAGE CHANGEOVER DEVICE FOR SELECTIVELY FEEDING A FIRST SUPPLY VOLTAGE OF A SECOND SUPPLY VOLTAGE TO A CIRCUIT PORTION DEPENDING ON A GIVEN CRITERION Nov 15, 2000 Abandoned
Array ( [id] => 1460350 [patent_doc_number] => 06426666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'Diode-assisted gate turn-off thyristor' [patent_app_type] => B1 [patent_app_number] => 09/708505 [patent_app_country] => US [patent_app_date] => 2000-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 4520 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426666.pdf [firstpage_image] =>[orig_patent_app_number] => 09708505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/708505
Diode-assisted gate turn-off thyristor Nov 8, 2000 Issued
Array ( [id] => 4342799 [patent_doc_number] => 06333646 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Abnormal clock detector and abnormal clock detecting apparatus' [patent_app_type] => 1 [patent_app_number] => 9/705082 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 8506 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 408 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333646.pdf [firstpage_image] =>[orig_patent_app_number] => 705082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/705082
Abnormal clock detector and abnormal clock detecting apparatus Nov 2, 2000 Issued
Array ( [id] => 1019088 [patent_doc_number] => 06891430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-10 [patent_title] => 'Techniques for signal measurement using a conditionally stable amplifier' [patent_app_type] => utility [patent_app_number] => 09/695706 [patent_app_country] => US [patent_app_date] => 2000-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 5551 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891430.pdf [firstpage_image] =>[orig_patent_app_number] => 09695706 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/695706
Techniques for signal measurement using a conditionally stable amplifier Oct 24, 2000 Issued
Array ( [id] => 4320209 [patent_doc_number] => 06316967 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Current detector' [patent_app_type] => 1 [patent_app_number] => 9/692144 [patent_app_country] => US [patent_app_date] => 2000-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7765 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316967.pdf [firstpage_image] =>[orig_patent_app_number] => 692144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/692144
Current detector Oct 19, 2000 Issued
Array ( [id] => 1597902 [patent_doc_number] => 06384660 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Clock control circuit and method' [patent_app_type] => B1 [patent_app_number] => 09/688370 [patent_app_country] => US [patent_app_date] => 2000-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 8259 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384660.pdf [firstpage_image] =>[orig_patent_app_number] => 09688370 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/688370
Clock control circuit and method Oct 11, 2000 Issued
Array ( [id] => 1548372 [patent_doc_number] => 06445245 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-03 [patent_title] => 'Digitally controlled impedance for I/O of an integrated circuit device' [patent_app_type] => B1 [patent_app_number] => 09/684539 [patent_app_country] => US [patent_app_date] => 2000-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 10464 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/445/06445245.pdf [firstpage_image] =>[orig_patent_app_number] => 09684539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/684539
Digitally controlled impedance for I/O of an integrated circuit device Oct 5, 2000 Issued
Array ( [id] => 4285030 [patent_doc_number] => 06281727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Fine-tuning phase-locked loop PLL using variable resistor between dual PLL loops' [patent_app_type] => 1 [patent_app_number] => 9/679684 [patent_app_country] => US [patent_app_date] => 2000-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281727.pdf [firstpage_image] =>[orig_patent_app_number] => 679684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/679684
Fine-tuning phase-locked loop PLL using variable resistor between dual PLL loops Oct 4, 2000 Issued
Array ( [id] => 1492256 [patent_doc_number] => 06417701 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-09 [patent_title] => 'Method and apparatus for identifying a waveform period' [patent_app_type] => B1 [patent_app_number] => 09/675243 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3650 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/417/06417701.pdf [firstpage_image] =>[orig_patent_app_number] => 09675243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675243
Method and apparatus for identifying a waveform period Sep 28, 2000 Issued
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