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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1544950 [patent_doc_number] => 06373312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Precision, high speed delay system for providing delayed clock edges with new delay values every clock period' [patent_app_type] => B1 [patent_app_number] => 09/672030 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 5154 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/373/06373312.pdf [firstpage_image] =>[orig_patent_app_number] => 09672030 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672030
Precision, high speed delay system for providing delayed clock edges with new delay values every clock period Sep 28, 2000 Issued
Array ( [id] => 1487433 [patent_doc_number] => 06366151 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Waveform correction circuit' [patent_app_type] => B1 [patent_app_number] => 09/675638 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/366/06366151.pdf [firstpage_image] =>[orig_patent_app_number] => 09675638 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675638
Waveform correction circuit Sep 28, 2000 Issued
Array ( [id] => 1597893 [patent_doc_number] => 06384658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-07 [patent_title] => 'Clock splitter circuit to generate synchronized clock and inverted clock' [patent_app_type] => B1 [patent_app_number] => 09/676313 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1945 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/384/06384658.pdf [firstpage_image] =>[orig_patent_app_number] => 09676313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/676313
Clock splitter circuit to generate synchronized clock and inverted clock Sep 28, 2000 Issued
Array ( [id] => 1554984 [patent_doc_number] => 06348828 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-19 [patent_title] => 'Clock enable circuit for use in a high speed reprogrammable delay line incorporating glitchless enable/disable functionality' [patent_app_type] => B1 [patent_app_number] => 09/672903 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2326 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/348/06348828.pdf [firstpage_image] =>[orig_patent_app_number] => 09672903 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672903
Clock enable circuit for use in a high speed reprogrammable delay line incorporating glitchless enable/disable functionality Sep 28, 2000 Issued
Array ( [id] => 1598425 [patent_doc_number] => 06492843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Random frequency clock generator' [patent_app_type] => B1 [patent_app_number] => 09/675501 [patent_app_country] => US [patent_app_date] => 2000-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4578 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492843.pdf [firstpage_image] =>[orig_patent_app_number] => 09675501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/675501
Random frequency clock generator Sep 28, 2000 Issued
Array ( [id] => 1442282 [patent_doc_number] => 06335650 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages' [patent_app_type] => B1 [patent_app_number] => 09/670829 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1832 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335650.pdf [firstpage_image] =>[orig_patent_app_number] => 09670829 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670829
Method and apparatus for adjusting time delays in circuits with multiple operating supply voltages Sep 27, 2000 Issued
Array ( [id] => 4415328 [patent_doc_number] => 06300812 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Process, voltage, and temperature insensitive two phase clock generation circuit' [patent_app_type] => 1 [patent_app_number] => 9/672340 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3607 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300812.pdf [firstpage_image] =>[orig_patent_app_number] => 672340 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672340
Process, voltage, and temperature insensitive two phase clock generation circuit Sep 27, 2000 Issued
Array ( [id] => 717650 [patent_doc_number] => 07053673 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Versatile charge sampling circuits' [patent_app_type] => utility [patent_app_number] => 09/672803 [patent_app_country] => US [patent_app_date] => 2000-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 27 [patent_no_of_words] => 6173 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/053/07053673.pdf [firstpage_image] =>[orig_patent_app_number] => 09672803 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/672803
Versatile charge sampling circuits Sep 27, 2000 Issued
Array ( [id] => 4336578 [patent_doc_number] => 06320432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Output buffer circuit' [patent_app_type] => 1 [patent_app_number] => 9/670577 [patent_app_country] => US [patent_app_date] => 2000-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 9590 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/320/06320432.pdf [firstpage_image] =>[orig_patent_app_number] => 670577 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/670577
Output buffer circuit Sep 26, 2000 Issued
Array ( [id] => 1525161 [patent_doc_number] => 06353347 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Power control circuit for a line driver' [patent_app_type] => B1 [patent_app_number] => 09/663280 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4504 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/353/06353347.pdf [firstpage_image] =>[orig_patent_app_number] => 09663280 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/663280
Power control circuit for a line driver Sep 14, 2000 Issued
Array ( [id] => 1551366 [patent_doc_number] => 06346847 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-02-12 [patent_title] => 'Electronic circuit and corresponding method for trimming an IC' [patent_app_type] => B1 [patent_app_number] => 09/660775 [patent_app_country] => US [patent_app_date] => 2000-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3941 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/346/06346847.pdf [firstpage_image] =>[orig_patent_app_number] => 09660775 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660775
Electronic circuit and corresponding method for trimming an IC Sep 12, 2000 Issued
Array ( [id] => 1481490 [patent_doc_number] => 06452431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Scheme for delay locked loop reset protection' [patent_app_type] => B1 [patent_app_number] => 09/649691 [patent_app_country] => US [patent_app_date] => 2000-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4982 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/452/06452431.pdf [firstpage_image] =>[orig_patent_app_number] => 09649691 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/649691
Scheme for delay locked loop reset protection Aug 27, 2000 Issued
Array ( [id] => 1448689 [patent_doc_number] => 06369632 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'CMOS switching circuitry' [patent_app_type] => B1 [patent_app_number] => 09/643064 [patent_app_country] => US [patent_app_date] => 2000-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1966 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369632.pdf [firstpage_image] =>[orig_patent_app_number] => 09643064 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/643064
CMOS switching circuitry Aug 20, 2000 Issued
Array ( [id] => 1448662 [patent_doc_number] => 06369625 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Phase locked loop circuit' [patent_app_type] => B1 [patent_app_number] => 09/638879 [patent_app_country] => US [patent_app_date] => 2000-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 7724 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369625.pdf [firstpage_image] =>[orig_patent_app_number] => 09638879 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/638879
Phase locked loop circuit Aug 14, 2000 Issued
Array ( [id] => 4387681 [patent_doc_number] => 06304112 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Integrated circuit provided with a fail-safe mode' [patent_app_type] => 1 [patent_app_number] => 9/635115 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1666 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 391 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304112.pdf [firstpage_image] =>[orig_patent_app_number] => 635115 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/635115
Integrated circuit provided with a fail-safe mode Aug 8, 2000 Issued
Array ( [id] => 4379057 [patent_doc_number] => 06288599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'High voltage input buffer made by a low voltage process and having a self-adjusting trigger point' [patent_app_type] => 1 [patent_app_number] => 9/634561 [patent_app_country] => US [patent_app_date] => 2000-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6694 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288599.pdf [firstpage_image] =>[orig_patent_app_number] => 634561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/634561
High voltage input buffer made by a low voltage process and having a self-adjusting trigger point Aug 8, 2000 Issued
Array ( [id] => 1448715 [patent_doc_number] => 06369640 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Zero crossing control structure for a bidirectional switch with a stable threshold' [patent_app_type] => B1 [patent_app_number] => 09/628199 [patent_app_country] => US [patent_app_date] => 2000-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4108 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 27 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369640.pdf [firstpage_image] =>[orig_patent_app_number] => 09628199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/628199
Zero crossing control structure for a bidirectional switch with a stable threshold Jul 27, 2000 Issued
Array ( [id] => 1460322 [patent_doc_number] => 06426656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-30 [patent_title] => 'High speed, low-power inter-chip transmission system' [patent_app_type] => B1 [patent_app_number] => 09/625650 [patent_app_country] => US [patent_app_date] => 2000-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 25 [patent_no_of_words] => 7459 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426656.pdf [firstpage_image] =>[orig_patent_app_number] => 09625650 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625650
High speed, low-power inter-chip transmission system Jul 25, 2000 Issued
Array ( [id] => 4390285 [patent_doc_number] => 06278307 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Method and apparatus for 50% duty-cycle programmable divided-down clock with even and odd divisor rates' [patent_app_type] => 1 [patent_app_number] => 9/624618 [patent_app_country] => US [patent_app_date] => 2000-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1222 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 333 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278307.pdf [firstpage_image] =>[orig_patent_app_number] => 624618 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/624618
Method and apparatus for 50% duty-cycle programmable divided-down clock with even and odd divisor rates Jul 23, 2000 Issued
Array ( [id] => 4375929 [patent_doc_number] => 06275091 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Clock signal control circuit and method and synchronous delay circuit' [patent_app_type] => 1 [patent_app_number] => 9/620378 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8842 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275091.pdf [firstpage_image] =>[orig_patent_app_number] => 620378 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/620378
Clock signal control circuit and method and synchronous delay circuit Jul 19, 2000 Issued
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