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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1603445 [patent_doc_number] => 06433627 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'GTLone-one/zero-zero detector' [patent_app_type] => B1 [patent_app_number] => 09/621312 [patent_app_country] => US [patent_app_date] => 2000-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 25 [patent_no_of_words] => 6318 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/433/06433627.pdf [firstpage_image] =>[orig_patent_app_number] => 09621312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/621312
GTLone-one/zero-zero detector Jul 19, 2000 Issued
Array ( [id] => 1448692 [patent_doc_number] => 06369633 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Quadrature signal generation system' [patent_app_type] => B1 [patent_app_number] => 09/619637 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 3208 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369633.pdf [firstpage_image] =>[orig_patent_app_number] => 09619637 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/619637
Quadrature signal generation system Jul 18, 2000 Issued
Array ( [id] => 4387723 [patent_doc_number] => 06304115 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Phase locked loop having DC bias circuitry' [patent_app_type] => 1 [patent_app_number] => 9/618882 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4146 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/304/06304115.pdf [firstpage_image] =>[orig_patent_app_number] => 618882 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618882
Phase locked loop having DC bias circuitry Jul 18, 2000 Issued
Array ( [id] => 1588587 [patent_doc_number] => 06359484 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'Slew-rate-control structure for high-frequency operation' [patent_app_type] => B1 [patent_app_number] => 09/618961 [patent_app_country] => US [patent_app_date] => 2000-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4579 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359484.pdf [firstpage_image] =>[orig_patent_app_number] => 09618961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618961
Slew-rate-control structure for high-frequency operation Jul 18, 2000 Issued
Array ( [id] => 1598479 [patent_doc_number] => 06492858 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Semiconductor integrated circuit and method for generating a control signal therefor' [patent_app_type] => B1 [patent_app_number] => 09/618928 [patent_app_country] => US [patent_app_date] => 2000-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1845 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492858.pdf [firstpage_image] =>[orig_patent_app_number] => 09618928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618928
Semiconductor integrated circuit and method for generating a control signal therefor Jul 17, 2000 Issued
Array ( [id] => 4268350 [patent_doc_number] => 06259301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method and apparatus for selecting from multiple mixers' [patent_app_type] => 1 [patent_app_number] => 9/618109 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5907 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/259/06259301.pdf [firstpage_image] =>[orig_patent_app_number] => 618109 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/618109
Method and apparatus for selecting from multiple mixers Jul 16, 2000 Issued
Array ( [id] => 1423261 [patent_doc_number] => 06509789 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-21 [patent_title] => 'Circuit for reducing second and third order intermodulation distortion for a broadband RF amplifier' [patent_app_type] => B1 [patent_app_number] => 09/617610 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5375 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/509/06509789.pdf [firstpage_image] =>[orig_patent_app_number] => 09617610 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617610
Circuit for reducing second and third order intermodulation distortion for a broadband RF amplifier Jul 16, 2000 Issued
Array ( [id] => 4415033 [patent_doc_number] => 06310499 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Methods and apparatus for adjusting the deadtime between non-overlapping clock signals' [patent_app_type] => 1 [patent_app_number] => 9/617373 [patent_app_country] => US [patent_app_date] => 2000-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6133 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310499.pdf [firstpage_image] =>[orig_patent_app_number] => 617373 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617373
Methods and apparatus for adjusting the deadtime between non-overlapping clock signals Jul 16, 2000 Issued
Array ( [id] => 1448641 [patent_doc_number] => 06369619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Voltage tolerant input/output circuit' [patent_app_type] => B1 [patent_app_number] => 09/615959 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2515 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/369/06369619.pdf [firstpage_image] =>[orig_patent_app_number] => 09615959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/615959
Voltage tolerant input/output circuit Jul 13, 2000 Issued
Array ( [id] => 4320364 [patent_doc_number] => 06316977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Low charge-injection charge pump' [patent_app_type] => 1 [patent_app_number] => 9/617201 [patent_app_country] => US [patent_app_date] => 2000-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4029 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316977.pdf [firstpage_image] =>[orig_patent_app_number] => 617201 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/617201
Low charge-injection charge pump Jul 13, 2000 Issued
Array ( [id] => 7639590 [patent_doc_number] => 06396326 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'High voltage driver having overshoot/undershoot protection circuitry' [patent_app_type] => B1 [patent_app_number] => 09/607253 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4607 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396326.pdf [firstpage_image] =>[orig_patent_app_number] => 09607253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607253
High voltage driver having overshoot/undershoot protection circuitry Jun 29, 2000 Issued
Array ( [id] => 1006377 [patent_doc_number] => 06906557 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-06-14 [patent_title] => 'Fuse sense circuit' [patent_app_type] => utility [patent_app_number] => 09/607782 [patent_app_country] => US [patent_app_date] => 2000-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3180 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/906/06906557.pdf [firstpage_image] =>[orig_patent_app_number] => 09607782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/607782
Fuse sense circuit Jun 29, 2000 Issued
Array ( [id] => 1433616 [patent_doc_number] => 06340906 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Flip-flop control circuit, processor, and method for operating processor' [patent_app_type] => B1 [patent_app_number] => 09/605369 [patent_app_country] => US [patent_app_date] => 2000-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4531 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340906.pdf [firstpage_image] =>[orig_patent_app_number] => 09605369 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/605369
Flip-flop control circuit, processor, and method for operating processor Jun 28, 2000 Issued
Array ( [id] => 4280657 [patent_doc_number] => 06323712 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Delay circuit with voltage compensation' [patent_app_type] => 1 [patent_app_number] => 9/604066 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 7870 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323712.pdf [firstpage_image] =>[orig_patent_app_number] => 604066 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/604066
Delay circuit with voltage compensation Jun 25, 2000 Issued
Array ( [id] => 1433620 [patent_doc_number] => 06340910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Clock signal control method and circuit and data transmitting apparatus employing the same' [patent_app_type] => B1 [patent_app_number] => 09/603211 [patent_app_country] => US [patent_app_date] => 2000-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 27 [patent_no_of_words] => 8729 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340910.pdf [firstpage_image] =>[orig_patent_app_number] => 09603211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/603211
Clock signal control method and circuit and data transmitting apparatus employing the same Jun 25, 2000 Issued
Array ( [id] => 4415047 [patent_doc_number] => 06310500 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-30 [patent_title] => 'Race removal or reduction in latches and loops using phase skew' [patent_app_type] => 1 [patent_app_number] => 9/602206 [patent_app_country] => US [patent_app_date] => 2000-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 5901 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/310/06310500.pdf [firstpage_image] =>[orig_patent_app_number] => 602206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/602206
Race removal or reduction in latches and loops using phase skew Jun 22, 2000 Issued
Array ( [id] => 4425297 [patent_doc_number] => 06225831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Phase detector' [patent_app_type] => 1 [patent_app_number] => 9/586646 [patent_app_country] => US [patent_app_date] => 2000-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2925 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225831.pdf [firstpage_image] =>[orig_patent_app_number] => 586646 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/586646
Phase detector Jun 4, 2000 Issued
Array ( [id] => 1497952 [patent_doc_number] => 06404257 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Variable delay element for jitter control in high speed data links' [patent_app_type] => B1 [patent_app_number] => 09/584028 [patent_app_country] => US [patent_app_date] => 2000-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2772 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/404/06404257.pdf [firstpage_image] =>[orig_patent_app_number] => 09584028 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/584028
Variable delay element for jitter control in high speed data links May 29, 2000 Issued
Array ( [id] => 4326579 [patent_doc_number] => 06249154 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Process of controlling a switch of a switched-capacitance device, and corresponding switched-capacitance device' [patent_app_type] => 1 [patent_app_number] => 9/571392 [patent_app_country] => US [patent_app_date] => 2000-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5583 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249154.pdf [firstpage_image] =>[orig_patent_app_number] => 571392 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/571392
Process of controlling a switch of a switched-capacitance device, and corresponding switched-capacitance device May 14, 2000 Issued
Array ( [id] => 1462156 [patent_doc_number] => 06392451 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Threshold value operation circuit, and, and gate circuit, self hold circuit, start signal generation circuit using threshold value operation circuit' [patent_app_type] => B1 [patent_app_number] => 09/485456 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 32 [patent_no_of_words] => 15989 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/392/06392451.pdf [firstpage_image] =>[orig_patent_app_number] => 09485456 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/485456
Threshold value operation circuit, and, and gate circuit, self hold circuit, start signal generation circuit using threshold value operation circuit Apr 30, 2000 Issued
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