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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4267384 [patent_doc_number] => 06204709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Unlimited phase tracking delay locked loop' [patent_app_type] => 1 [patent_app_number] => 9/409539 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3702 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204709.pdf [firstpage_image] =>[orig_patent_app_number] => 409539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/409539
Unlimited phase tracking delay locked loop Sep 29, 1999 Issued
Array ( [id] => 4424175 [patent_doc_number] => 06194958 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-27 [patent_title] => 'Filter having minimized cut-off frequency variations' [patent_app_type] => 1 [patent_app_number] => 9/410155 [patent_app_country] => US [patent_app_date] => 1999-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3775 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/194/06194958.pdf [firstpage_image] =>[orig_patent_app_number] => 410155 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/410155
Filter having minimized cut-off frequency variations Sep 29, 1999 Issued
Array ( [id] => 4284869 [patent_doc_number] => 06281715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Low voltage differential signaling driver with pre-emphasis circuit' [patent_app_type] => 1 [patent_app_number] => 9/408773 [patent_app_country] => US [patent_app_date] => 1999-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6058 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281715.pdf [firstpage_image] =>[orig_patent_app_number] => 408773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/408773
Low voltage differential signaling driver with pre-emphasis circuit Sep 28, 1999 Issued
Array ( [id] => 4280711 [patent_doc_number] => 06323716 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Signal distributing circuit and signal line connecting method' [patent_app_type] => 1 [patent_app_number] => 9/401331 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 5100 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/323/06323716.pdf [firstpage_image] =>[orig_patent_app_number] => 401331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401331
Signal distributing circuit and signal line connecting method Sep 22, 1999 Issued
Array ( [id] => 4375658 [patent_doc_number] => 06275073 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-14 [patent_title] => 'Differential input circuit' [patent_app_type] => 1 [patent_app_number] => 9/401304 [patent_app_country] => US [patent_app_date] => 1999-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2502 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/275/06275073.pdf [firstpage_image] =>[orig_patent_app_number] => 401304 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/401304
Differential input circuit Sep 22, 1999 Issued
Array ( [id] => 4367233 [patent_doc_number] => 06191636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Input buffer/level shifter' [patent_app_type] => 1 [patent_app_number] => 9/400685 [patent_app_country] => US [patent_app_date] => 1999-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2475 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191636.pdf [firstpage_image] =>[orig_patent_app_number] => 400685 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400685
Input buffer/level shifter Sep 21, 1999 Issued
Array ( [id] => 4326898 [patent_doc_number] => 06249173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Temperature stabilizing circuit' [patent_app_type] => 1 [patent_app_number] => 9/400273 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 2878 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249173.pdf [firstpage_image] =>[orig_patent_app_number] => 400273 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400273
Temperature stabilizing circuit Sep 20, 1999 Issued
Array ( [id] => 1516602 [patent_doc_number] => 06420913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Dynamic termination logic driver with improved impedance control' [patent_app_type] => B1 [patent_app_number] => 09/398868 [patent_app_country] => US [patent_app_date] => 1999-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16423 [patent_no_of_claims] => 48 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420913.pdf [firstpage_image] =>[orig_patent_app_number] => 09398868 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398868
Dynamic termination logic driver with improved impedance control Sep 19, 1999 Issued
Array ( [id] => 4416060 [patent_doc_number] => 06265918 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-24 [patent_title] => 'Clock signal processing circuit and semiconductor device in which a clock signal is processed in improved method' [patent_app_type] => 1 [patent_app_number] => 9/389748 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 39 [patent_no_of_words] => 7177 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/265/06265918.pdf [firstpage_image] =>[orig_patent_app_number] => 389748 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389748
Clock signal processing circuit and semiconductor device in which a clock signal is processed in improved method Sep 6, 1999 Issued
Array ( [id] => 1472270 [patent_doc_number] => 06407611 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-18 [patent_title] => 'System and method for providing automatic compensation of IC design parameters that vary as a result of natural process variation' [patent_app_type] => B1 [patent_app_number] => 09/382298 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3373 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/407/06407611.pdf [firstpage_image] =>[orig_patent_app_number] => 09382298 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382298
System and method for providing automatic compensation of IC design parameters that vary as a result of natural process variation Aug 23, 1999 Issued
Array ( [id] => 4110771 [patent_doc_number] => 06100722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Phase detector with extended linear range' [patent_app_type] => 1 [patent_app_number] => 9/362478 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2146 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100722.pdf [firstpage_image] =>[orig_patent_app_number] => 362478 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362478
Phase detector with extended linear range Jul 27, 1999 Issued
Array ( [id] => 4368784 [patent_doc_number] => 06255874 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Transistor channel width and slew rate correction circuit and method' [patent_app_type] => 1 [patent_app_number] => 9/363699 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6154 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255874.pdf [firstpage_image] =>[orig_patent_app_number] => 363699 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/363699
Transistor channel width and slew rate correction circuit and method Jul 27, 1999 Issued
Array ( [id] => 4285196 [patent_doc_number] => 06281739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Fuse circuit and redundant decoder' [patent_app_type] => 1 [patent_app_number] => 9/347418 [patent_app_country] => US [patent_app_date] => 1999-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 7015 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281739.pdf [firstpage_image] =>[orig_patent_app_number] => 347418 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/347418
Fuse circuit and redundant decoder Jul 5, 1999 Issued
Array ( [id] => 4285003 [patent_doc_number] => 06281725 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-28 [patent_title] => 'Semiconductor integrated circuit having a clock recovery circuit' [patent_app_type] => 1 [patent_app_number] => 9/337421 [patent_app_country] => US [patent_app_date] => 1999-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 44 [patent_no_of_words] => 24016 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/281/06281725.pdf [firstpage_image] =>[orig_patent_app_number] => 337421 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/337421
Semiconductor integrated circuit having a clock recovery circuit Jun 21, 1999 Issued
Array ( [id] => 4425328 [patent_doc_number] => 06225842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Control device with forced operation function and semiconductor integrated circuit device' [patent_app_type] => 1 [patent_app_number] => 9/319930 [patent_app_country] => US [patent_app_date] => 1999-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3582 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225842.pdf [firstpage_image] =>[orig_patent_app_number] => 319930 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/319930
Control device with forced operation function and semiconductor integrated circuit device Jun 16, 1999 Issued
Array ( [id] => 4416148 [patent_doc_number] => 06229362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Charge pump for adaptively controlling current offset' [patent_app_type] => 1 [patent_app_number] => 9/334134 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 29 [patent_no_of_words] => 6352 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 367 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/229/06229362.pdf [firstpage_image] =>[orig_patent_app_number] => 334134 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334134
Charge pump for adaptively controlling current offset Jun 14, 1999 Issued
Array ( [id] => 4342981 [patent_doc_number] => 06333659 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-25 [patent_title] => 'Clock control method and circuit' [patent_app_type] => 1 [patent_app_number] => 9/330162 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 59 [patent_no_of_words] => 13387 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/333/06333659.pdf [firstpage_image] =>[orig_patent_app_number] => 330162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/330162
Clock control method and circuit Jun 10, 1999 Issued
Array ( [id] => 4245303 [patent_doc_number] => 06144251 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Semiconductor integrated circuit device having component circuits free from through-current in transition period between active mode and sleep mode' [patent_app_type] => 1 [patent_app_number] => 9/329253 [patent_app_country] => US [patent_app_date] => 1999-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10470 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144251.pdf [firstpage_image] =>[orig_patent_app_number] => 329253 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/329253
Semiconductor integrated circuit device having component circuits free from through-current in transition period between active mode and sleep mode Jun 9, 1999 Issued
Array ( [id] => 4097284 [patent_doc_number] => 06133780 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Digitally tunable voltage reference using a neuron MOSFET' [patent_app_type] => 1 [patent_app_number] => 9/326166 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2268 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133780.pdf [firstpage_image] =>[orig_patent_app_number] => 326166 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326166
Digitally tunable voltage reference using a neuron MOSFET Jun 3, 1999 Issued
Array ( [id] => 4414578 [patent_doc_number] => 06239635 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Self-timing control circuit' [patent_app_type] => 1 [patent_app_number] => 9/325555 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 14494 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/239/06239635.pdf [firstpage_image] =>[orig_patent_app_number] => 325555 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325555
Self-timing control circuit Jun 3, 1999 Issued
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