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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4303979 [patent_doc_number] => 06198321 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Device for the generation of a drive signal phase-shifted with respect to an external synchronization' [patent_app_type] => 1 [patent_app_number] => 9/326438 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5881 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198321.pdf [firstpage_image] =>[orig_patent_app_number] => 326438 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/326438
Device for the generation of a drive signal phase-shifted with respect to an external synchronization Jun 3, 1999 Issued
Array ( [id] => 4390213 [patent_doc_number] => 06278302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Digital power-up reset circuit' [patent_app_type] => 1 [patent_app_number] => 9/324922 [patent_app_country] => US [patent_app_date] => 1999-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2675 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/278/06278302.pdf [firstpage_image] =>[orig_patent_app_number] => 324922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324922
Digital power-up reset circuit Jun 2, 1999 Issued
Array ( [id] => 4245117 [patent_doc_number] => 06144240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Low noise buffer circuit for increasing digital signal transition slew rates' [patent_app_type] => 1 [patent_app_number] => 9/323308 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2478 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144240.pdf [firstpage_image] =>[orig_patent_app_number] => 323308 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323308
Low noise buffer circuit for increasing digital signal transition slew rates May 31, 1999 Issued
Array ( [id] => 4255853 [patent_doc_number] => 06137326 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Clock signal producing device' [patent_app_type] => 1 [patent_app_number] => 9/323780 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2969 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137326.pdf [firstpage_image] =>[orig_patent_app_number] => 323780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323780
Clock signal producing device May 31, 1999 Issued
Array ( [id] => 4165297 [patent_doc_number] => 06157235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Quadrature signal generator and method therefor' [patent_app_type] => 1 [patent_app_number] => 9/324598 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1283 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157235.pdf [firstpage_image] =>[orig_patent_app_number] => 324598 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/324598
Quadrature signal generator and method therefor May 31, 1999 Issued
Array ( [id] => 4389130 [patent_doc_number] => 06294937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-25 [patent_title] => 'Method and apparatus for self correcting parallel I/O circuitry' [patent_app_type] => 1 [patent_app_number] => 9/322329 [patent_app_country] => US [patent_app_date] => 1999-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 28 [patent_no_of_words] => 12133 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/294/06294937.pdf [firstpage_image] =>[orig_patent_app_number] => 322329 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/322329
Method and apparatus for self correcting parallel I/O circuitry May 24, 1999 Issued
Array ( [id] => 1433614 [patent_doc_number] => 06340904 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal' [patent_app_type] => B1 [patent_app_number] => 09/317059 [patent_app_country] => US [patent_app_date] => 1999-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2801 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340904.pdf [firstpage_image] =>[orig_patent_app_number] => 09317059 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/317059
Method and apparatus for generating an internal clock signal that is synchronized to an external clock signal May 23, 1999 Issued
Array ( [id] => 4363181 [patent_doc_number] => 06201424 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Synchronous clock generator including a delay-locked loop signal loss detector' [patent_app_type] => 1 [patent_app_number] => 9/316076 [patent_app_country] => US [patent_app_date] => 1999-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4018 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201424.pdf [firstpage_image] =>[orig_patent_app_number] => 316076 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/316076
Synchronous clock generator including a delay-locked loop signal loss detector May 19, 1999 Issued
Array ( [id] => 4424341 [patent_doc_number] => 06177813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Low frequency detection circuit' [patent_app_type] => 1 [patent_app_number] => 9/311588 [patent_app_country] => US [patent_app_date] => 1999-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 23 [patent_no_of_words] => 2987 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177813.pdf [firstpage_image] =>[orig_patent_app_number] => 311588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311588
Low frequency detection circuit May 13, 1999 Issued
Array ( [id] => 4303910 [patent_doc_number] => 06184747 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Differential filter with gyrator' [patent_app_type] => 1 [patent_app_number] => 9/311105 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5884 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184747.pdf [firstpage_image] =>[orig_patent_app_number] => 311105 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311105
Differential filter with gyrator May 12, 1999 Issued
Array ( [id] => 4304083 [patent_doc_number] => 06198328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Circuit configuration for producing complementary signals' [patent_app_type] => 1 [patent_app_number] => 9/311120 [patent_app_country] => US [patent_app_date] => 1999-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1863 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/198/06198328.pdf [firstpage_image] =>[orig_patent_app_number] => 311120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/311120
Circuit configuration for producing complementary signals May 12, 1999 Issued
Array ( [id] => 4363379 [patent_doc_number] => 06218885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Circuit and method for providing temperature stability in an FM quadrature detector' [patent_app_type] => 1 [patent_app_number] => 9/309529 [patent_app_country] => US [patent_app_date] => 1999-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 1553 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218885.pdf [firstpage_image] =>[orig_patent_app_number] => 309529 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/309529
Circuit and method for providing temperature stability in an FM quadrature detector May 10, 1999 Issued
Array ( [id] => 4368839 [patent_doc_number] => 06255878 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Dual path asynchronous delay circuit' [patent_app_type] => 1 [patent_app_number] => 9/307533 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4527 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255878.pdf [firstpage_image] =>[orig_patent_app_number] => 307533 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307533
Dual path asynchronous delay circuit May 6, 1999 Issued
Array ( [id] => 4255954 [patent_doc_number] => 06137333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Optimal delay controller' [patent_app_type] => 1 [patent_app_number] => 9/307588 [patent_app_country] => US [patent_app_date] => 1999-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3481 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137333.pdf [firstpage_image] =>[orig_patent_app_number] => 307588 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/307588
Optimal delay controller May 6, 1999 Issued
Array ( [id] => 4091495 [patent_doc_number] => 06163185 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Phase frequency detector having instantaneous phase difference output' [patent_app_type] => 1 [patent_app_number] => 9/304597 [patent_app_country] => US [patent_app_date] => 1999-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1558 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163185.pdf [firstpage_image] =>[orig_patent_app_number] => 304597 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304597
Phase frequency detector having instantaneous phase difference output May 3, 1999 Issued
Array ( [id] => 4240891 [patent_doc_number] => 06075388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Phase detector with extended linear range' [patent_app_type] => 1 [patent_app_number] => 9/302213 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1942 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/075/06075388.pdf [firstpage_image] =>[orig_patent_app_number] => 302213 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/302213
Phase detector with extended linear range Apr 28, 1999 Issued
Array ( [id] => 4246168 [patent_doc_number] => 06166569 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Test interface circuits with waveform synthesizers having reduced spurious signals' [patent_app_type] => 1 [patent_app_number] => 9/298362 [patent_app_country] => US [patent_app_date] => 1999-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3961 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/166/06166569.pdf [firstpage_image] =>[orig_patent_app_number] => 298362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298362
Test interface circuits with waveform synthesizers having reduced spurious signals Apr 22, 1999 Issued
Array ( [id] => 4165363 [patent_doc_number] => 06114886 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Output buffer circuit' [patent_app_type] => 1 [patent_app_number] => 9/294400 [patent_app_country] => US [patent_app_date] => 1999-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4412 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 256 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114886.pdf [firstpage_image] =>[orig_patent_app_number] => 294400 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294400
Output buffer circuit Apr 19, 1999 Issued
Array ( [id] => 4296656 [patent_doc_number] => 06211719 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Power control circuit for a line driver' [patent_app_type] => 1 [patent_app_number] => 9/294131 [patent_app_country] => US [patent_app_date] => 1999-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4502 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211719.pdf [firstpage_image] =>[orig_patent_app_number] => 294131 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/294131
Power control circuit for a line driver Apr 18, 1999 Issued
Array ( [id] => 4303612 [patent_doc_number] => 06184727 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Write driver circuit having enhanced switching control circuitry' [patent_app_type] => 1 [patent_app_number] => 9/292294 [patent_app_country] => US [patent_app_date] => 1999-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5620 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184727.pdf [firstpage_image] =>[orig_patent_app_number] => 292294 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292294
Write driver circuit having enhanced switching control circuitry Apr 14, 1999 Issued
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