
My Trang Ton
Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2504 |
| Total Applications | 1512 |
| Issued Applications | 1345 |
| Pending Applications | 95 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
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[patent_title] => 'Method for improving the efficiency of discharging capacitive loads in H-bridge switching networks'
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Array
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[patent_issue_date] => 2000-09-12
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Array
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[patent_issue_date] => 2000-03-07
[patent_title] => 'Clock circuit employable for sequential regulation systems having multiple functions'
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Array
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Array
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Array
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Array
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Array
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[patent_title] => 'Current switch and PLL in which it is used'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/024058 | Current switch and PLL in which it is used | Feb 16, 1998 | Issued |
| 90/004917 | VEHICLE MIRROR | Feb 16, 1998 | Issued |
Array
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[patent_title] => 'Interconnect structure for FPGA using a multiplexer'
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Array
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[patent_title] => 'Selectively configurable analog signal sampler'
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Array
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[patent_title] => 'Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential'
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Array
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Array
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Array
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Array
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Array
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Array
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Array
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