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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4225199 [patent_doc_number] => 06087863 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for improving the efficiency of discharging capacitive loads in H-bridge switching networks' [patent_app_type] => 1 [patent_app_number] => 9/039429 [patent_app_country] => US [patent_app_date] => 1998-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 1900 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087863.pdf [firstpage_image] =>[orig_patent_app_number] => 039429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/039429
Method for improving the efficiency of discharging capacitive loads in H-bridge switching networks Mar 15, 1998 Issued
Array ( [id] => 4241531 [patent_doc_number] => 06118317 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Clock synchronizing system and synchronizing method' [patent_app_type] => 1 [patent_app_number] => 9/038967 [patent_app_country] => US [patent_app_date] => 1998-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2059 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118317.pdf [firstpage_image] =>[orig_patent_app_number] => 038967 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038967
Clock synchronizing system and synchronizing method Mar 11, 1998 Issued
Array ( [id] => 4139259 [patent_doc_number] => 06034559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Clock circuit employable for sequential regulation systems having multiple functions' [patent_app_type] => 1 [patent_app_number] => 9/038237 [patent_app_country] => US [patent_app_date] => 1998-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2698 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034559.pdf [firstpage_image] =>[orig_patent_app_number] => 038237 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/038237
Clock circuit employable for sequential regulation systems having multiple functions Mar 10, 1998 Issued
Array ( [id] => 4302705 [patent_doc_number] => 06181177 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Baseline correction circuit for PWM data readback systems' [patent_app_type] => 1 [patent_app_number] => 9/030104 [patent_app_country] => US [patent_app_date] => 1998-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6957 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/181/06181177.pdf [firstpage_image] =>[orig_patent_app_number] => 030104 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/030104
Baseline correction circuit for PWM data readback systems Feb 24, 1998 Issued
Array ( [id] => 3920074 [patent_doc_number] => 06002281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Delay locked loop' [patent_app_type] => 1 [patent_app_number] => 9/026864 [patent_app_country] => US [patent_app_date] => 1998-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3792 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002281.pdf [firstpage_image] =>[orig_patent_app_number] => 026864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026864
Delay locked loop Feb 19, 1998 Issued
Array ( [id] => 4148114 [patent_doc_number] => 06060947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Hybrid IC device with wide dynamic range' [patent_app_type] => 1 [patent_app_number] => 9/025864 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 8236 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060947.pdf [firstpage_image] =>[orig_patent_app_number] => 025864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/025864
Hybrid IC device with wide dynamic range Feb 18, 1998 Issued
Array ( [id] => 4154245 [patent_doc_number] => 06064245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Dynamic circuit for capturing data with wide reset tolerance' [patent_app_type] => 1 [patent_app_number] => 9/026087 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2386 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064245.pdf [firstpage_image] =>[orig_patent_app_number] => 026087 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/026087
Dynamic circuit for capturing data with wide reset tolerance Feb 18, 1998 Issued
Array ( [id] => 4154215 [patent_doc_number] => 06064243 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-16 [patent_title] => 'Current switch and PLL in which it is used' [patent_app_type] => 1 [patent_app_number] => 9/024058 [patent_app_country] => US [patent_app_date] => 1998-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 5804 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/064/06064243.pdf [firstpage_image] =>[orig_patent_app_number] => 024058 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/024058
Current switch and PLL in which it is used Feb 16, 1998 Issued
90/004917 VEHICLE MIRROR Feb 16, 1998 Issued
Array ( [id] => 3941441 [patent_doc_number] => 05939930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Interconnect structure for FPGA using a multiplexer' [patent_app_type] => 1 [patent_app_number] => 9/023367 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3138 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939930.pdf [firstpage_image] =>[orig_patent_app_number] => 023367 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023367
Interconnect structure for FPGA using a multiplexer Feb 12, 1998 Issued
Array ( [id] => 4149780 [patent_doc_number] => 06031399 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Selectively configurable analog signal sampler' [patent_app_type] => 1 [patent_app_number] => 9/023681 [patent_app_country] => US [patent_app_date] => 1998-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 49 [patent_no_of_words] => 4056 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/031/06031399.pdf [firstpage_image] =>[orig_patent_app_number] => 023681 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/023681
Selectively configurable analog signal sampler Feb 12, 1998 Issued
Array ( [id] => 4303769 [patent_doc_number] => 06184738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential' [patent_app_type] => 1 [patent_app_number] => 9/019199 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 6455 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184738.pdf [firstpage_image] =>[orig_patent_app_number] => 019199 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019199
Input buffer for supplying semiconductor device with internal signal based on comparison of external signal with reference potential Feb 4, 1998 Issued
Array ( [id] => 4139220 [patent_doc_number] => 06034556 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-07 [patent_title] => 'Sample-and-hold circuit including operational amplifier as an input circuit' [patent_app_type] => 1 [patent_app_number] => 9/019363 [patent_app_country] => US [patent_app_date] => 1998-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 7192 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/034/06034556.pdf [firstpage_image] =>[orig_patent_app_number] => 019363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/019363
Sample-and-hold circuit including operational amplifier as an input circuit Feb 4, 1998 Issued
Array ( [id] => 4110628 [patent_doc_number] => 06052016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Charge and discharge control circuit' [patent_app_type] => 1 [patent_app_number] => 9/018074 [patent_app_country] => US [patent_app_date] => 1998-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3743 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052016.pdf [firstpage_image] =>[orig_patent_app_number] => 018074 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/018074
Charge and discharge control circuit Feb 2, 1998 Issued
Array ( [id] => 4255896 [patent_doc_number] => 06137329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Load voltage slew-rate controller' [patent_app_type] => 1 [patent_app_number] => 9/014073 [patent_app_country] => US [patent_app_date] => 1998-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3756 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/137/06137329.pdf [firstpage_image] =>[orig_patent_app_number] => 014073 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/014073
Load voltage slew-rate controller Jan 26, 1998 Issued
Array ( [id] => 4378957 [patent_doc_number] => 06288592 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-11 [patent_title] => 'Cable driver with controlled linear rise and fall' [patent_app_type] => 1 [patent_app_number] => 9/010194 [patent_app_country] => US [patent_app_date] => 1998-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 6016 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/288/06288592.pdf [firstpage_image] =>[orig_patent_app_number] => 010194 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010194
Cable driver with controlled linear rise and fall Jan 20, 1998 Issued
Array ( [id] => 4205144 [patent_doc_number] => 06014047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Method and apparatus for phase rotation in a phase locked loop' [patent_app_type] => 1 [patent_app_number] => 9/004133 [patent_app_country] => US [patent_app_date] => 1998-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4270 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/014/06014047.pdf [firstpage_image] =>[orig_patent_app_number] => 004133 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/004133
Method and apparatus for phase rotation in a phase locked loop Jan 6, 1998 Issued
Array ( [id] => 4140041 [patent_doc_number] => 06147551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Switched capacitor circuit and method for reducing sampling noise' [patent_app_type] => 1 [patent_app_number] => 9/002789 [patent_app_country] => US [patent_app_date] => 1998-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 15850 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147551.pdf [firstpage_image] =>[orig_patent_app_number] => 002789 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002789
Switched capacitor circuit and method for reducing sampling noise Jan 4, 1998 Issued
Array ( [id] => 4112771 [patent_doc_number] => 06023182 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'High gain pulse generator circuit with clock gating' [patent_app_type] => 1 [patent_app_number] => 9/002148 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 5094 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023182.pdf [firstpage_image] =>[orig_patent_app_number] => 002148 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002148
High gain pulse generator circuit with clock gating Dec 30, 1997 Issued
Array ( [id] => 4134603 [patent_doc_number] => 06127856 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-03 [patent_title] => 'Sample-and-hold circuit operable at a low voltage' [patent_app_type] => 1 [patent_app_number] => 8/998383 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2570 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/127/06127856.pdf [firstpage_image] =>[orig_patent_app_number] => 998383 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/998383
Sample-and-hold circuit operable at a low voltage Dec 23, 1997 Issued
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