My Trang Ton

Array ( [id] => 3950595 [patent_doc_number] => 05982220 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'High speed multiplexer circuit' [patent_app_type] => 1 [patent_app_number] => 8/998031 [patent_app_country] => US [patent_app_date] => 1997-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1258 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982220.pdf [firstpage_image] =>[orig_patent_app_number] => 998031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4241618 [patent_doc_number] => 06118323 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Electrostatic discharge protection circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/996734 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4179 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/118/06118323.pdf [firstpage_image] =>[orig_patent_app_number] => 996734 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3982782 [patent_doc_number] => 05917364 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Bi-directional interface circuit of reduced signal alteration' [patent_app_type] => 1 [patent_app_number] => 8/997664 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3552 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917364.pdf [firstpage_image] =>[orig_patent_app_number] => 997664 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4163931 [patent_doc_number] => 06104228 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Phase aligner system and method' [patent_app_type] => 1 [patent_app_number] => 8/997084 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 43 [patent_no_of_words] => 5428 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/104/06104228.pdf [firstpage_image] =>[orig_patent_app_number] => 997084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4160886 [patent_doc_number] => 06124750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Current sensing gated current source for delay reduction in a universal serial bus (USB) low speed output driver' [patent_app_type] => 1 [patent_app_number] => 8/995494 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2090 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/124/06124750.pdf [firstpage_image] =>[orig_patent_app_number] => 995494 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4365315 [patent_doc_number] => 06169429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'HDD chip set partitioning' [patent_app_type] => 1 [patent_app_number] => 8/994714 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 941 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169429.pdf [firstpage_image] =>[orig_patent_app_number] => 994714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4245037 [patent_doc_number] => 06144234 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-07 [patent_title] => 'Sample hold circuit and semiconductor device having the same' [patent_app_type] => 1 [patent_app_number] => 8/994999 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 3717 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/144/06144234.pdf [firstpage_image] =>[orig_patent_app_number] => 994999 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3941162 [patent_doc_number] => 05939910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Digital device for initializing an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/994193 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4388 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939910.pdf [firstpage_image] =>[orig_patent_app_number] => 994193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3987006 [patent_doc_number] => 05949258 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-07 [patent_title] => 'Data holding circuit' [patent_app_type] => 1 [patent_app_number] => 8/987198 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 17 [patent_no_of_words] => 1488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/949/05949258.pdf [firstpage_image] =>[orig_patent_app_number] => 987198 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3982652 [patent_doc_number] => 05917358 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-29 [patent_title] => 'Method and output buffer with programmable bias to accommodate multiple supply voltages' [patent_app_type] => 1 [patent_app_number] => 8/987361 [patent_app_country] => US [patent_app_date] => 1997-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 8820 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/917/05917358.pdf [firstpage_image] =>[orig_patent_app_number] => 987361 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4192897 [patent_doc_number] => 06094090 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Differential amplifier circuit, CMOS inverter, demodulator circuit for pulse-width modulation, and sampling circuit' [patent_app_type] => 1 [patent_app_number] => 8/980259 [patent_app_country] => US [patent_app_date] => 1997-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 41 [patent_no_of_words] => 20642 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094090.pdf [firstpage_image] =>[orig_patent_app_number] => 980259 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3934431 [patent_doc_number] => 05952877 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Integrated resistor for continuous time signal processing applications' [patent_app_type] => 1 [patent_app_number] => 8/976330 [patent_app_country] => US [patent_app_date] => 1997-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2743 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952877.pdf [firstpage_image] =>[orig_patent_app_number] => 976330 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4165438 [patent_doc_number] => 06114890 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Skew-reduction circuit' [patent_app_type] => 1 [patent_app_number] => 8/967658 [patent_app_country] => US [patent_app_date] => 1997-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 77 [patent_figures_cnt] => 160 [patent_no_of_words] => 40063 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/114/06114890.pdf [firstpage_image] =>[orig_patent_app_number] => 967658 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3931683 [patent_doc_number] => 05945872 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'Two-phase boosted CMOS switch drive technique and circuit' [patent_app_type] => 1 [patent_app_number] => 8/965267 [patent_app_country] => US [patent_app_date] => 1997-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8489 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945872.pdf [firstpage_image] =>[orig_patent_app_number] => 965267 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4082127 [patent_doc_number] => 05966044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-12 [patent_title] => 'Pull-up circuit and semiconductor device using the same' [patent_app_type] => 1 [patent_app_number] => 8/964461 [patent_app_country] => US [patent_app_date] => 1997-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 5921 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/966/05966044.pdf [firstpage_image] =>[orig_patent_app_number] => 964461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015128 [patent_doc_number] => 05889418 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Frequency detector of phase locked loop' [patent_app_type] => 1 [patent_app_number] => 8/962520 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 37 [patent_no_of_words] => 4187 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889418.pdf [firstpage_image] =>[orig_patent_app_number] => 962520 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4005569 [patent_doc_number] => 05986497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Interface circuit for capacitive sensor' [patent_app_type] => 1 [patent_app_number] => 8/962357 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5018 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 275 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986497.pdf [firstpage_image] =>[orig_patent_app_number] => 962357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4110544 [patent_doc_number] => 06052010 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Circuit, apparatus and method for generating signals phase-separated by ninety degrees' [patent_app_type] => 1 [patent_app_number] => 8/957725 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 5221 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052010.pdf [firstpage_image] =>[orig_patent_app_number] => 957725 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3920046 [patent_doc_number] => 06002279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Clock recovery circuit' [patent_app_type] => 1 [patent_app_number] => 8/957694 [patent_app_country] => US [patent_app_date] => 1997-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 3939 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002279.pdf [firstpage_image] =>[orig_patent_app_number] => 957694 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4069201 [patent_doc_number] => 05896049 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Electrical signal frequency detector' [patent_app_type] => 1 [patent_app_number] => 8/955077 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3190 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/896/05896049.pdf [firstpage_image] =>[orig_patent_app_number] => 955077 [rel_patent_id] =>[rel_patent_doc_number] =>)