My Trang Ton

Array ( [id] => 3946474 [patent_doc_number] => 05973518 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-26 [patent_title] => 'Low voltage sample and hold circuit' [patent_app_type] => 1 [patent_app_number] => 8/953187 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7755 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/973/05973518.pdf [firstpage_image] =>[orig_patent_app_number] => 953187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950385 [patent_doc_number] => 05982205 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Low voltage sample and hold circuits' [patent_app_type] => 1 [patent_app_number] => 8/953551 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7786 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/982/05982205.pdf [firstpage_image] =>[orig_patent_app_number] => 953551 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4189372 [patent_doc_number] => 06020769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Low voltage sample and hold circuits' [patent_app_type] => 1 [patent_app_number] => 8/953188 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 7725 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020769.pdf [firstpage_image] =>[orig_patent_app_number] => 953188 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4105109 [patent_doc_number] => 06049242 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Voltage reference source for an overvoltage-tolerant bus interface' [patent_app_type] => 1 [patent_app_number] => 8/949861 [patent_app_country] => US [patent_app_date] => 1997-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 2959 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049242.pdf [firstpage_image] =>[orig_patent_app_number] => 949861 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4092621 [patent_doc_number] => 06025751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Self-bootstrapping word-line driver circuit and method' [patent_app_type] => 1 [patent_app_number] => 8/947754 [patent_app_country] => US [patent_app_date] => 1997-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1975 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/025/06025751.pdf [firstpage_image] =>[orig_patent_app_number] => 947754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029196 [patent_doc_number] => 05926058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Aperture compensation circuit and RGB monitor' [patent_app_type] => 1 [patent_app_number] => 8/944962 [patent_app_country] => US [patent_app_date] => 1997-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 7366 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926058.pdf [firstpage_image] =>[orig_patent_app_number] => 944962 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4000724 [patent_doc_number] => 05920212 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-06 [patent_title] => 'Control-type continuous ramp converting apparatus and method therefore' [patent_app_type] => 1 [patent_app_number] => 8/941105 [patent_app_country] => US [patent_app_date] => 1997-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 1838 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/920/05920212.pdf [firstpage_image] =>[orig_patent_app_number] => 941105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3941537 [patent_doc_number] => 05939937 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Constant current CMOS output driver circuit with dual gate transistor devices' [patent_app_type] => 1 [patent_app_number] => 8/940862 [patent_app_country] => US [patent_app_date] => 1997-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 6616 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 397 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939937.pdf [firstpage_image] =>[orig_patent_app_number] => 940862 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3893351 [patent_doc_number] => 05894235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-13 [patent_title] => 'High speed data sampling system' [patent_app_type] => 1 [patent_app_number] => 8/936775 [patent_app_country] => US [patent_app_date] => 1997-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 5497 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/894/05894235.pdf [firstpage_image] =>[orig_patent_app_number] => 936775 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4028974 [patent_doc_number] => 05926044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Clock switching device and method' [patent_app_type] => 1 [patent_app_number] => 8/933103 [patent_app_country] => US [patent_app_date] => 1997-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4300 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926044.pdf [firstpage_image] =>[orig_patent_app_number] => 933103 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3963562 [patent_doc_number] => 05936456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Output driver circuit in semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/934510 [patent_app_country] => US [patent_app_date] => 1997-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4042 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936456.pdf [firstpage_image] =>[orig_patent_app_number] => 934510 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4112795 [patent_doc_number] => 06023184 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-08 [patent_title] => 'Converter providing digital scaling and mixing' [patent_app_type] => 1 [patent_app_number] => 8/975901 [patent_app_country] => US [patent_app_date] => 1997-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3358 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/023/06023184.pdf [firstpage_image] =>[orig_patent_app_number] => 975901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050300 [patent_doc_number] => 05909133 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Clock signal modeling circuit' [patent_app_type] => 1 [patent_app_number] => 8/927812 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3724 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909133.pdf [firstpage_image] =>[orig_patent_app_number] => 927812 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3991925 [patent_doc_number] => 05959479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Sampling timebase system' [patent_app_type] => 1 [patent_app_number] => 8/927972 [patent_app_country] => US [patent_app_date] => 1997-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2732 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959479.pdf [firstpage_image] =>[orig_patent_app_number] => 927972 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3952912 [patent_doc_number] => 05990707 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Method and system for sliced integration of flash analog to digital converters in read channel circuits' [patent_app_type] => 1 [patent_app_number] => 8/927122 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 14777 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/990/05990707.pdf [firstpage_image] =>[orig_patent_app_number] => 927122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943258 [patent_doc_number] => 05929689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Photodetector quiescent current compensation method and apparatus' [patent_app_type] => 1 [patent_app_number] => 8/924609 [patent_app_country] => US [patent_app_date] => 1997-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 6729 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929689.pdf [firstpage_image] =>[orig_patent_app_number] => 924609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4015171 [patent_doc_number] => 05889421 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Device for detecting the locking of an automatic gain control circuit' [patent_app_type] => 1 [patent_app_number] => 8/922612 [patent_app_country] => US [patent_app_date] => 1997-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4108 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889421.pdf [firstpage_image] =>[orig_patent_app_number] => 922612 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029014 [patent_doc_number] => 05926047 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Synchronous clock generator including a delay-locked loop signal loss detector' [patent_app_type] => 1 [patent_app_number] => 8/921237 [patent_app_country] => US [patent_app_date] => 1997-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4018 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926047.pdf [firstpage_image] =>[orig_patent_app_number] => 921237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4050584 [patent_doc_number] => 05912581 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Spurious-emission-reducing terminal configuration for an integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/919455 [patent_app_country] => US [patent_app_date] => 1997-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4379 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912581.pdf [firstpage_image] =>[orig_patent_app_number] => 919455 [rel_patent_id] =>[rel_patent_doc_number] =>)