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Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )

Most Active Art Unit
2816
Art Unit(s)
3992, 2816, 2504
Total Applications
1512
Issued Applications
1345
Pending Applications
95
Abandoned Applications
73

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3991802 [patent_doc_number] => 05959470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Operational amplifier with two sample and hold circuits' [patent_app_type] => 1 [patent_app_number] => 8/917994 [patent_app_country] => US [patent_app_date] => 1997-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 5907 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/959/05959470.pdf [firstpage_image] =>[orig_patent_app_number] => 917994 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917994
Operational amplifier with two sample and hold circuits Aug 24, 1997 Issued
Array ( [id] => 4214230 [patent_doc_number] => 06028462 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Tunable delay for very high speed' [patent_app_type] => 1 [patent_app_number] => 8/916819 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 4977 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028462.pdf [firstpage_image] =>[orig_patent_app_number] => 916819 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/916819
Tunable delay for very high speed Aug 21, 1997 Issued
Array ( [id] => 4050440 [patent_doc_number] => 05909143 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Circuit for determining and storing an average signal value' [patent_app_type] => 1 [patent_app_number] => 8/912831 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1733 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909143.pdf [firstpage_image] =>[orig_patent_app_number] => 912831 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912831
Circuit for determining and storing an average signal value Aug 18, 1997 Issued
Array ( [id] => 4050354 [patent_doc_number] => 05909137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Voltage adder/subtractor circuit with two differential transistor pairs' [patent_app_type] => 1 [patent_app_number] => 8/914167 [patent_app_country] => US [patent_app_date] => 1997-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 6248 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909137.pdf [firstpage_image] =>[orig_patent_app_number] => 914167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914167
Voltage adder/subtractor circuit with two differential transistor pairs Aug 18, 1997 Issued
Array ( [id] => 3955686 [patent_doc_number] => 05999021 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Pad signal detecting circuit in a semiconductor device for detecting a reference voltage in a high-speed interface' [patent_app_type] => 1 [patent_app_number] => 8/912654 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3248 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999021.pdf [firstpage_image] =>[orig_patent_app_number] => 912654 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912654
Pad signal detecting circuit in a semiconductor device for detecting a reference voltage in a high-speed interface Aug 17, 1997 Issued
Array ( [id] => 4125422 [patent_doc_number] => 06072342 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Timed one-shot active termination device' [patent_app_type] => 1 [patent_app_number] => 8/907933 [patent_app_country] => US [patent_app_date] => 1997-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5032 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/072/06072342.pdf [firstpage_image] =>[orig_patent_app_number] => 907933 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/907933
Timed one-shot active termination device Aug 10, 1997 Issued
Array ( [id] => 4029114 [patent_doc_number] => 05926052 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Variable phase shifter and method' [patent_app_type] => 1 [patent_app_number] => 8/908827 [patent_app_country] => US [patent_app_date] => 1997-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 4487 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926052.pdf [firstpage_image] =>[orig_patent_app_number] => 908827 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/908827
Variable phase shifter and method Aug 7, 1997 Issued
Array ( [id] => 4071861 [patent_doc_number] => 05867058 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'Method and system for enhancing a digitally sampled voltage input waveform' [patent_app_type] => 1 [patent_app_number] => 8/904902 [patent_app_country] => US [patent_app_date] => 1997-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4520 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/867/05867058.pdf [firstpage_image] =>[orig_patent_app_number] => 904902 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/904902
Method and system for enhancing a digitally sampled voltage input waveform Jul 31, 1997 Issued
Array ( [id] => 3963187 [patent_doc_number] => 05936431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Input signal variation detection circuit' [patent_app_type] => 1 [patent_app_number] => 8/903430 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 3352 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936431.pdf [firstpage_image] =>[orig_patent_app_number] => 903430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903430
Input signal variation detection circuit Jul 29, 1997 Issued
Array ( [id] => 4050059 [patent_doc_number] => 05874841 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Sample-and-hold circuit for a switched-mode power supply' [patent_app_type] => 1 [patent_app_number] => 8/901491 [patent_app_country] => US [patent_app_date] => 1997-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2944 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874841.pdf [firstpage_image] =>[orig_patent_app_number] => 901491 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/901491
Sample-and-hold circuit for a switched-mode power supply Jul 27, 1997 Issued
Array ( [id] => 3963521 [patent_doc_number] => 05936453 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Circuit arrangement for controlling a pulse output stage' [patent_app_type] => 1 [patent_app_number] => 8/875285 [patent_app_country] => US [patent_app_date] => 1997-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1321 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/936/05936453.pdf [firstpage_image] =>[orig_patent_app_number] => 875285 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/875285
Circuit arrangement for controlling a pulse output stage Jul 22, 1997 Issued
Array ( [id] => 4050134 [patent_doc_number] => 05874845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Non-overlapping clock phase splitter' [patent_app_type] => 1 [patent_app_number] => 8/897860 [patent_app_country] => US [patent_app_date] => 1997-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3831 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 311 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874845.pdf [firstpage_image] =>[orig_patent_app_number] => 897860 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/897860
Non-overlapping clock phase splitter Jul 20, 1997 Issued
Array ( [id] => 3943199 [patent_doc_number] => 05929685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Mode setting circuit' [patent_app_type] => 1 [patent_app_number] => 8/896756 [patent_app_country] => US [patent_app_date] => 1997-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2102 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/929/05929685.pdf [firstpage_image] =>[orig_patent_app_number] => 896756 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/896756
Mode setting circuit Jul 17, 1997 Issued
Array ( [id] => 4019820 [patent_doc_number] => 05963081 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-10-05 [patent_title] => 'Circuit arrangement having at least two signal paths' [patent_app_type] => 1 [patent_app_number] => 8/914051 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 8062 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/963/05963081.pdf [firstpage_image] =>[orig_patent_app_number] => 914051 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914051
Circuit arrangement having at least two signal paths Jul 14, 1997 Issued
Array ( [id] => 4050073 [patent_doc_number] => 05874842 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Sample and hold circuit having quick resetting function' [patent_app_type] => 1 [patent_app_number] => 8/914067 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3487 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/874/05874842.pdf [firstpage_image] =>[orig_patent_app_number] => 914067 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/914067
Sample and hold circuit having quick resetting function Jul 14, 1997 Issued
Array ( [id] => 3955900 [patent_doc_number] => 05999036 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Output circuit with output voltage controlled by current flow through an output transistor circuit' [patent_app_type] => 1 [patent_app_number] => 8/892974 [patent_app_country] => US [patent_app_date] => 1997-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 2881 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/999/05999036.pdf [firstpage_image] =>[orig_patent_app_number] => 892974 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892974
Output circuit with output voltage controlled by current flow through an output transistor circuit Jul 14, 1997 Issued
Array ( [id] => 3934786 [patent_doc_number] => 05877649 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Circuit arrangement for setting the operating point' [patent_app_type] => 1 [patent_app_number] => 8/889851 [patent_app_country] => US [patent_app_date] => 1997-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1431 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877649.pdf [firstpage_image] =>[orig_patent_app_number] => 889851 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/889851
Circuit arrangement for setting the operating point Jul 7, 1997 Issued
Array ( [id] => 4059256 [patent_doc_number] => 05933042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Active quench circuit for an avalanche current device' [patent_app_type] => 1 [patent_app_number] => 8/886300 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 4623 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933042.pdf [firstpage_image] =>[orig_patent_app_number] => 886300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886300
Active quench circuit for an avalanche current device Jun 30, 1997 Issued
Array ( [id] => 4015158 [patent_doc_number] => 05889420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'OCD with low output capacitance' [patent_app_type] => 1 [patent_app_number] => 8/885329 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2782 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889420.pdf [firstpage_image] =>[orig_patent_app_number] => 885329 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885329
OCD with low output capacitance Jun 29, 1997 Issued
Array ( [id] => 4015310 [patent_doc_number] => 05889431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-30 [patent_title] => 'Current mode transistor circuit method' [patent_app_type] => 1 [patent_app_number] => 8/883223 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6112 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/889/05889431.pdf [firstpage_image] =>[orig_patent_app_number] => 883223 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883223
Current mode transistor circuit method Jun 25, 1997 Issued
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