
My Trang Ton
Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2504 |
| Total Applications | 1512 |
| Issued Applications | 1345 |
| Pending Applications | 95 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4063447
[patent_doc_number] => 05864248
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-26
[patent_title] => 'Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver'
[patent_app_type] => 1
[patent_app_number] => 8/746847
[patent_app_country] => US
[patent_app_date] => 1996-11-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 4363
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/864/05864248.pdf
[firstpage_image] =>[orig_patent_app_number] => 746847
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/746847 | Phase-locked loop circuit for reproducing clock signals synchronized with transmitter in receiver | Nov 17, 1996 | Issued |
Array
(
[id] => 4192931
[patent_doc_number] => 06094091
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-25
[patent_title] => 'Interface circuit capable of preventing reflected waves and glitches'
[patent_app_type] => 1
[patent_app_number] => 8/746648
[patent_app_country] => US
[patent_app_date] => 1996-11-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 6010
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[patent_words_short_claim] => 88
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/094/06094091.pdf
[firstpage_image] =>[orig_patent_app_number] => 746648
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/746648 | Interface circuit capable of preventing reflected waves and glitches | Nov 12, 1996 | Issued |
Array
(
[id] => 3854131
[patent_doc_number] => 05719523
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-17
[patent_title] => 'Threshold correcting reference voltage generator'
[patent_app_type] => 1
[patent_app_number] => 8/747985
[patent_app_country] => US
[patent_app_date] => 1996-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2109
[patent_no_of_claims] => 19
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[patent_words_short_claim] => 172
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[pdf_file] => patents/05/719/05719523.pdf
[firstpage_image] =>[orig_patent_app_number] => 747985
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/747985 | Threshold correcting reference voltage generator | Nov 11, 1996 | Issued |
Array
(
[id] => 4032483
[patent_doc_number] => 05883534
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'Waveform shaping device and clock supply apparatus'
[patent_app_type] => 1
[patent_app_number] => 8/747076
[patent_app_country] => US
[patent_app_date] => 1996-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 30
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[patent_no_of_words] => 24533
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[pdf_file] => patents/05/883/05883534.pdf
[firstpage_image] =>[orig_patent_app_number] => 747076
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/747076 | Waveform shaping device and clock supply apparatus | Nov 7, 1996 | Issued |
Array
(
[id] => 4040707
[patent_doc_number] => 05994937
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Temperature and power supply adjusted address transition detector'
[patent_app_type] => 1
[patent_app_number] => 8/744810
[patent_app_country] => US
[patent_app_date] => 1996-11-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2649
[patent_no_of_claims] => 15
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994937.pdf
[firstpage_image] =>[orig_patent_app_number] => 744810
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/744810 | Temperature and power supply adjusted address transition detector | Nov 5, 1996 | Issued |
| 08/740838 | LOW POWER WAKE-UP SYSTEM AND METHOD | Nov 3, 1996 | Abandoned |
Array
(
[id] => 3847339
[patent_doc_number] => 05847586
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-08
[patent_title] => 'Enhanced power-on-reset/low voltage detection circuit'
[patent_app_type] => 1
[patent_app_number] => 8/741741
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/05/847/05847586.pdf
[firstpage_image] =>[orig_patent_app_number] => 741741
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741741 | Enhanced power-on-reset/low voltage detection circuit | Oct 30, 1996 | Issued |
Array
(
[id] => 4040824
[patent_doc_number] => 05994946
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Alternating inverters for capacitive coupling reduction in transmission lines'
[patent_app_type] => 1
[patent_app_number] => 8/742109
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2642
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994946.pdf
[firstpage_image] =>[orig_patent_app_number] => 742109
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742109 | Alternating inverters for capacitive coupling reduction in transmission lines | Oct 30, 1996 | Issued |
Array
(
[id] => 3882285
[patent_doc_number] => 05825210
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Symmetrical phase-frequency detector'
[patent_app_type] => 1
[patent_app_number] => 8/738805
[patent_app_country] => US
[patent_app_date] => 1996-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2928
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/825/05825210.pdf
[firstpage_image] =>[orig_patent_app_number] => 738805
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/738805 | Symmetrical phase-frequency detector | Oct 27, 1996 | Issued |
Array
(
[id] => 3989209
[patent_doc_number] => 05861765
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-19
[patent_title] => 'Analogue delay circuit with a constant delay time'
[patent_app_type] => 1
[patent_app_number] => 8/720690
[patent_app_country] => US
[patent_app_date] => 1996-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3217
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[pdf_file] => patents/05/861/05861765.pdf
[firstpage_image] =>[orig_patent_app_number] => 720690
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/720690 | Analogue delay circuit with a constant delay time | Oct 1, 1996 | Issued |
Array
(
[id] => 3822603
[patent_doc_number] => 05770965
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-23
[patent_title] => 'Circuit and method of compensating for non-linearities in a sensor signal'
[patent_app_type] => 1
[patent_app_number] => 8/722407
[patent_app_country] => US
[patent_app_date] => 1996-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/770/05770965.pdf
[firstpage_image] =>[orig_patent_app_number] => 722407
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/722407 | Circuit and method of compensating for non-linearities in a sensor signal | Sep 29, 1996 | Issued |
Array
(
[id] => 3654310
[patent_doc_number] => 05684422
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Pipelined microprocessor including a high speed single-clock latch circuit'
[patent_app_type] => 1
[patent_app_number] => 8/722902
[patent_app_country] => US
[patent_app_date] => 1996-09-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/684/05684422.pdf
[firstpage_image] =>[orig_patent_app_number] => 722902
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/722902 | Pipelined microprocessor including a high speed single-clock latch circuit | Sep 26, 1996 | Issued |
Array
(
[id] => 4032467
[patent_doc_number] => 05883533
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-16
[patent_title] => 'Clock signal generating device having a redundant configuration'
[patent_app_type] => 1
[patent_app_number] => 8/721615
[patent_app_country] => US
[patent_app_date] => 1996-09-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/883/05883533.pdf
[firstpage_image] =>[orig_patent_app_number] => 721615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721615 | Clock signal generating device having a redundant configuration | Sep 25, 1996 | Issued |
Array
(
[id] => 3837867
[patent_doc_number] => 05739716
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-14
[patent_title] => 'Programmable analog switch'
[patent_app_type] => 1
[patent_app_number] => 8/718264
[patent_app_country] => US
[patent_app_date] => 1996-09-20
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/739/05739716.pdf
[firstpage_image] =>[orig_patent_app_number] => 718264
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/718264 | Programmable analog switch | Sep 19, 1996 | Issued |
Array
(
[id] => 3768714
[patent_doc_number] => 05844431
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Low noise low power CMOS correlated double sampler'
[patent_app_type] => 1
[patent_app_number] => 8/715201
[patent_app_country] => US
[patent_app_date] => 1996-09-18
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/844/05844431.pdf
[firstpage_image] =>[orig_patent_app_number] => 715201
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/715201 | Low noise low power CMOS correlated double sampler | Sep 17, 1996 | Issued |
Array
(
[id] => 3747358
[patent_doc_number] => 05786712
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-28
[patent_title] => 'Fast differential sample-and-hold circuit'
[patent_app_type] => 1
[patent_app_number] => 8/704606
[patent_app_country] => US
[patent_app_date] => 1996-09-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/786/05786712.pdf
[firstpage_image] =>[orig_patent_app_number] => 704606
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/704606 | Fast differential sample-and-hold circuit | Sep 15, 1996 | Issued |
Array
(
[id] => 4042666
[patent_doc_number] => 05856752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-01-05
[patent_title] => 'Driver circuit with precharge and active hold'
[patent_app_type] => 1
[patent_app_number] => 8/710230
[patent_app_country] => US
[patent_app_date] => 1996-09-13
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[pdf_file] => patents/05/856/05856752.pdf
[firstpage_image] =>[orig_patent_app_number] => 710230
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/710230 | Driver circuit with precharge and active hold | Sep 12, 1996 | Issued |
Array
(
[id] => 3831797
[patent_doc_number] => 05731726
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-24
[patent_title] => 'Controllable precision on-chip delay element'
[patent_app_type] => 1
[patent_app_number] => 8/725192
[patent_app_country] => US
[patent_app_date] => 1996-09-13
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[pdf_file] => patents/05/731/05731726.pdf
[firstpage_image] =>[orig_patent_app_number] => 725192
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/725192 | Controllable precision on-chip delay element | Sep 12, 1996 | Issued |
Array
(
[id] => 4004866
[patent_doc_number] => 05923208
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-13
[patent_title] => 'Low voltage temperature-to-voltage converter'
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[patent_app_number] => 8/713574
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[pdf_file] => patents/05/923/05923208.pdf
[firstpage_image] =>[orig_patent_app_number] => 713574
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/713574 | Low voltage temperature-to-voltage converter | Sep 11, 1996 | Issued |
Array
(
[id] => 3734555
[patent_doc_number] => 05703512
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-30
[patent_title] => 'Method and apparatus for test mode entry during power up'
[patent_app_type] => 1
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[pdf_file] => patents/05/703/05703512.pdf
[firstpage_image] =>[orig_patent_app_number] => 712960
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/712960 | Method and apparatus for test mode entry during power up | Sep 11, 1996 | Issued |