My Trang Ton

Array ( [id] => 3882496 [patent_doc_number] => 05825225 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-20 [patent_title] => 'Boosted differential latch' [patent_app_type] => 1 [patent_app_number] => 8/599029 [patent_app_country] => US [patent_app_date] => 1996-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1944 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/825/05825225.pdf [firstpage_image] =>[orig_patent_app_number] => 599029 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3737501 [patent_doc_number] => 05666078 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-09 [patent_title] => 'Programmable impedance output driver' [patent_app_type] => 1 [patent_app_number] => 8/597655 [patent_app_country] => US [patent_app_date] => 1996-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2200 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/666/05666078.pdf [firstpage_image] =>[orig_patent_app_number] => 597655 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4104992 [patent_doc_number] => 06049235 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-11 [patent_title] => 'Semiconductor device, signal processing system using the same, and calculation method therefor' [patent_app_type] => 1 [patent_app_number] => 8/595657 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 11549 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/049/06049235.pdf [firstpage_image] =>[orig_patent_app_number] => 595657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3737502 [patent_doc_number] => 05694062 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-02 [patent_title] => 'Self-timed phase detector and method' [patent_app_type] => 1 [patent_app_number] => 8/595854 [patent_app_country] => US [patent_app_date] => 1996-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 6040 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/694/05694062.pdf [firstpage_image] =>[orig_patent_app_number] => 595854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3703669 [patent_doc_number] => 05661679 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-26 [patent_title] => 'Delay circuit having a plurality of memory cells and corresponding control circuits for controlling the movement of a signal through the memory cells' [patent_app_type] => 1 [patent_app_number] => 8/595090 [patent_app_country] => US [patent_app_date] => 1996-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3820 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/661/05661679.pdf [firstpage_image] =>[orig_patent_app_number] => 595090 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3894519 [patent_doc_number] => 05777505 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'Low-power crosspoint switch' [patent_app_type] => 1 [patent_app_number] => 8/591738 [patent_app_country] => US [patent_app_date] => 1996-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4753 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/777/05777505.pdf [firstpage_image] =>[orig_patent_app_number] => 591738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4029181 [patent_doc_number] => 05926057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Semiconductor device, circuit having the device, and correlation calculation apparatus, signal converter, and signal processing system utilizing the circuit' [patent_app_type] => 1 [patent_app_number] => 8/590505 [patent_app_country] => US [patent_app_date] => 1996-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 11080 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926057.pdf [firstpage_image] =>[orig_patent_app_number] => 590505 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3848603 [patent_doc_number] => 05708382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-13 [patent_title] => 'Clock signal modeling circuit' [patent_app_type] => 1 [patent_app_number] => 8/587745 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3725 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/708/05708382.pdf [firstpage_image] =>[orig_patent_app_number] => 587745 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3654380 [patent_doc_number] => 05684427 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Bipolar driver circuit including primary and pre-driver transistors' [patent_app_type] => 1 [patent_app_number] => 8/588060 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 10348 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684427.pdf [firstpage_image] =>[orig_patent_app_number] => 588060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3750175 [patent_doc_number] => 05801563 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Output driver circuitry having a single slew rate resistor' [patent_app_type] => 1 [patent_app_number] => 8/588988 [patent_app_country] => US [patent_app_date] => 1996-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2683 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/801/05801563.pdf [firstpage_image] =>[orig_patent_app_number] => 588988 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3742723 [patent_doc_number] => 05699002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Flip-flop circuit, and shift register circuit, serial-parallel converter and parallel-serial converter using the same' [patent_app_type] => 1 [patent_app_number] => 8/587476 [patent_app_country] => US [patent_app_date] => 1996-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14182 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 325 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699002.pdf [firstpage_image] =>[orig_patent_app_number] => 587476 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3742805 [patent_doc_number] => 05699007 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'High-speed solid state buffer circuit and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/583935 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4727 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 434 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699007.pdf [firstpage_image] =>[orig_patent_app_number] => 583935 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3931497 [patent_doc_number] => 05945860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-31 [patent_title] => 'CLM/ECL clock phase shifter with CMOS digital control' [patent_app_type] => 1 [patent_app_number] => 8/583169 [patent_app_country] => US [patent_app_date] => 1996-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4395 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/945/05945860.pdf [firstpage_image] =>[orig_patent_app_number] => 583169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3639694 [patent_doc_number] => 05631586 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-05-20 [patent_title] => 'Sine-wave generator circuit' [patent_app_type] => 1 [patent_app_number] => 8/582671 [patent_app_country] => US [patent_app_date] => 1996-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3430 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/631/05631586.pdf [firstpage_image] =>[orig_patent_app_number] => 582671 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3627205 [patent_doc_number] => 05689204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-18 [patent_title] => 'Clipper circuit for clipping an upper or lower portion of a uni-directional sinusoidal voltage signal' [patent_app_type] => 1 [patent_app_number] => 8/580415 [patent_app_country] => US [patent_app_date] => 1995-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2068 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/689/05689204.pdf [firstpage_image] =>[orig_patent_app_number] => 580415 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734443 [patent_doc_number] => 05703504 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Feedforward adaptive threshold processing method' [patent_app_type] => 1 [patent_app_number] => 8/578727 [patent_app_country] => US [patent_app_date] => 1995-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 1952 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703504.pdf [firstpage_image] =>[orig_patent_app_number] => 578727 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3752451 [patent_doc_number] => 05717352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-10 [patent_title] => 'Wave formatter circuit for semiconductor test system' [patent_app_type] => 1 [patent_app_number] => 8/577736 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 3 [patent_no_of_words] => 4826 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/717/05717352.pdf [firstpage_image] =>[orig_patent_app_number] => 577736 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3695450 [patent_doc_number] => 05604456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Differential RS latch circuit' [patent_app_type] => 1 [patent_app_number] => 8/576370 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4315 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 312 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604456.pdf [firstpage_image] =>[orig_patent_app_number] => 576370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3734428 [patent_doc_number] => 05670908 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-23 [patent_title] => 'Circuit for controlling output voltage from charge pump' [patent_app_type] => 1 [patent_app_number] => 8/576052 [patent_app_country] => US [patent_app_date] => 1995-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1136 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/670/05670908.pdf [firstpage_image] =>[orig_patent_app_number] => 576052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3782502 [patent_doc_number] => 05757209 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-26 [patent_title] => 'Extremum voltage supply circuit with improved switching' [patent_app_type] => 1 [patent_app_number] => 8/573898 [patent_app_country] => US [patent_app_date] => 1995-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2261 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/757/05757209.pdf [firstpage_image] =>[orig_patent_app_number] => 573898 [rel_patent_id] =>[rel_patent_doc_number] =>)