
My Trang Ton
Examiner (ID: 3916, Phone: (571)272-1754 , Office: P/3992 )
| Most Active Art Unit | 2816 |
| Art Unit(s) | 3992, 2816, 2504 |
| Total Applications | 1512 |
| Issued Applications | 1345 |
| Pending Applications | 95 |
| Abandoned Applications | 73 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3532308
[patent_doc_number] => 05541545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-30
[patent_title] => 'High speed bipolar D latch circuit with reduced latch clocking output corruption'
[patent_app_type] => 1
[patent_app_number] => 8/486327
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1189
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/541/05541545.pdf
[firstpage_image] =>[orig_patent_app_number] => 486327
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/486327 | High speed bipolar D latch circuit with reduced latch clocking output corruption | Jun 6, 1995 | Issued |
Array
(
[id] => 3598010
[patent_doc_number] => 05521547
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-05-28
[patent_title] => 'Boost voltage generating circuit'
[patent_app_type] => 1
[patent_app_number] => 8/485144
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 3494
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/521/05521547.pdf
[firstpage_image] =>[orig_patent_app_number] => 485144
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/485144 | Boost voltage generating circuit | Jun 6, 1995 | Issued |
Array
(
[id] => 3898110
[patent_doc_number] => 05834951
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'Current amplifier having a fully differential output without a d. c. bias and applications thereof'
[patent_app_type] => 1
[patent_app_number] => 8/487864
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 11
[patent_no_of_words] => 5289
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 209
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/834/05834951.pdf
[firstpage_image] =>[orig_patent_app_number] => 487864
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/487864 | Current amplifier having a fully differential output without a d. c. bias and applications thereof | Jun 6, 1995 | Issued |
Array
(
[id] => 3555896
[patent_doc_number] => 05572155
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-05
[patent_title] => 'CCD signal read-out circuit free from ailiasing of high-frequency noises'
[patent_app_type] => 1
[patent_app_number] => 8/474670
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 36
[patent_no_of_words] => 9797
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/572/05572155.pdf
[firstpage_image] =>[orig_patent_app_number] => 474670
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/474670 | CCD signal read-out circuit free from ailiasing of high-frequency noises | Jun 6, 1995 | Issued |
Array
(
[id] => 3626013
[patent_doc_number] => 05614849
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-25
[patent_title] => 'Method of resetting a CMOS amplifier'
[patent_app_type] => 1
[patent_app_number] => 8/484812
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 5688
[patent_no_of_claims] => 6
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[patent_words_short_claim] => 114
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/614/05614849.pdf
[firstpage_image] =>[orig_patent_app_number] => 484812
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/484812 | Method of resetting a CMOS amplifier | Jun 6, 1995 | Issued |
Array
(
[id] => 3639869
[patent_doc_number] => 05631598
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-05-20
[patent_title] => 'Frequency compensation for a low drop-out regulator'
[patent_app_type] => 1
[patent_app_number] => 8/488403
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2993
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 3
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/631/05631598.pdf
[firstpage_image] =>[orig_patent_app_number] => 488403
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/488403 | Frequency compensation for a low drop-out regulator | Jun 6, 1995 | Issued |
Array
(
[id] => 3512723
[patent_doc_number] => 05570056
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-29
[patent_title] => 'Bipolar analog multipliers for low voltage applications'
[patent_app_type] => 1
[patent_app_number] => 8/485088
[patent_app_country] => US
[patent_app_date] => 1995-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 3468
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 509
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/570/05570056.pdf
[firstpage_image] =>[orig_patent_app_number] => 485088
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/485088 | Bipolar analog multipliers for low voltage applications | Jun 6, 1995 | Issued |
Array
(
[id] => 3654339
[patent_doc_number] => 05684424
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-04
[patent_title] => 'Pulse skew control'
[patent_app_type] => 1
[patent_app_number] => 8/468726
[patent_app_country] => US
[patent_app_date] => 1995-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 5472
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/684/05684424.pdf
[firstpage_image] =>[orig_patent_app_number] => 468726
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/468726 | Pulse skew control | Jun 5, 1995 | Issued |
| 08/466107 | METHOD AND APPARATUS FOR TEST MODE ENTRY DURING POWER UP | Jun 5, 1995 | Abandoned |
Array
(
[id] => 3521235
[patent_doc_number] => 05576645
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'Sample and hold flip-flop for CMOS logic'
[patent_app_type] => 1
[patent_app_number] => 8/465669
[patent_app_country] => US
[patent_app_date] => 1995-06-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 10
[patent_no_of_words] => 3336
[patent_no_of_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/576/05576645.pdf
[firstpage_image] =>[orig_patent_app_number] => 465669
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/465669 | Sample and hold flip-flop for CMOS logic | Jun 4, 1995 | Issued |
Array
(
[id] => 3653360
[patent_doc_number] => 05638018
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-10
[patent_title] => 'P-type flip-flop'
[patent_app_type] => 1
[patent_app_number] => 8/459786
[patent_app_country] => US
[patent_app_date] => 1995-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 4399
[patent_no_of_claims] => 8
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/638/05638018.pdf
[firstpage_image] =>[orig_patent_app_number] => 459786
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/459786 | P-type flip-flop | Jun 1, 1995 | Issued |
Array
(
[id] => 3672801
[patent_doc_number] => 05598296
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-01-28
[patent_title] => 'Prismatic telescope optical system'
[patent_app_type] => 1
[patent_app_number] => 8/458063
[patent_app_country] => US
[patent_app_date] => 1995-06-01
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/598/05598296.pdf
[firstpage_image] =>[orig_patent_app_number] => 458063
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/458063 | Prismatic telescope optical system | May 31, 1995 | Issued |
Array
(
[id] => 3823132
[patent_doc_number] => 05789956
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Low power flip-flop'
[patent_app_type] => 1
[patent_app_number] => 8/451875
[patent_app_country] => US
[patent_app_date] => 1995-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/789/05789956.pdf
[firstpage_image] =>[orig_patent_app_number] => 451875
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/451875 | Low power flip-flop | May 25, 1995 | Issued |
| 08/452628 | PRECISION ON-CHIP DELAY ELEMENT | May 24, 1995 | Abandoned |
Array
(
[id] => 3521430
[patent_doc_number] => 05576654
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-19
[patent_title] => 'BIMOS driver circuit and method'
[patent_app_type] => 1
[patent_app_number] => 8/441726
[patent_app_country] => US
[patent_app_date] => 1995-05-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1639
[patent_no_of_claims] => 20
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/576/05576654.pdf
[firstpage_image] =>[orig_patent_app_number] => 441726
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/441726 | BIMOS driver circuit and method | May 15, 1995 | Issued |
| 08/431933 | THRESHOLD CORRECTING REFERENCE VOLTAGE GENERATOR | Apr 30, 1995 | Abandoned |
Array
(
[id] => 3593664
[patent_doc_number] => 05550503
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-27
[patent_title] => 'Circuits and method for reducing voltage error when charging and discharging a capacitor through a transmission gate'
[patent_app_type] => 1
[patent_app_number] => 8/430999
[patent_app_country] => US
[patent_app_date] => 1995-04-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5362
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/550/05550503.pdf
[firstpage_image] =>[orig_patent_app_number] => 430999
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/430999 | Circuits and method for reducing voltage error when charging and discharging a capacitor through a transmission gate | Apr 27, 1995 | Issued |
Array
(
[id] => 3558894
[patent_doc_number] => 05574392
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-11-12
[patent_title] => 'Asymmetrical ramp generator system'
[patent_app_type] => 1
[patent_app_number] => 8/428374
[patent_app_country] => US
[patent_app_date] => 1995-04-25
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/574/05574392.pdf
[firstpage_image] =>[orig_patent_app_number] => 428374
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428374 | Asymmetrical ramp generator system | Apr 24, 1995 | Issued |
Array
(
[id] => 3643323
[patent_doc_number] => 05610773
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-11
[patent_title] => 'Actuated mirror array and method for the manufacture thereof'
[patent_app_type] => 1
[patent_app_number] => 8/428757
[patent_app_country] => US
[patent_app_date] => 1995-04-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 3713
[patent_no_of_claims] => 18
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/610/05610773.pdf
[firstpage_image] =>[orig_patent_app_number] => 428757
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428757 | Actuated mirror array and method for the manufacture thereof | Apr 24, 1995 | Issued |
Array
(
[id] => 3592144
[patent_doc_number] => 05552732
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'High speed divide by 1.5 clock generator'
[patent_app_type] => 1
[patent_app_number] => 8/428589
[patent_app_country] => US
[patent_app_date] => 1995-04-25
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/552/05552732.pdf
[firstpage_image] =>[orig_patent_app_number] => 428589
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/428589 | High speed divide by 1.5 clock generator | Apr 24, 1995 | Issued |