My Trang Ton

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Array ( [id] => 3461097 [patent_doc_number] => 05402011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Current source circuit' [patent_app_type] => 1 [patent_app_number] => 8/079407 [patent_app_country] => US [patent_app_date] => 1993-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 11 [patent_no_of_words] => 3825 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402011.pdf [firstpage_image] =>[orig_patent_app_number] => 079407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3428617 [patent_doc_number] => 05459423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Semiconductor integrated circuit for a stable constant delay time' [patent_app_type] => 1 [patent_app_number] => 8/077737 [patent_app_country] => US [patent_app_date] => 1993-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 3355 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 34 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459423.pdf [firstpage_image] =>[orig_patent_app_number] => 077737 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3431460 [patent_doc_number] => 05404053 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-04 [patent_title] => 'Circuit for controlling the maximum current in a MOS power transistor used for driving a load connected to earth' [patent_app_type] => 1 [patent_app_number] => 8/075056 [patent_app_country] => US [patent_app_date] => 1993-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2359 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/404/05404053.pdf [firstpage_image] =>[orig_patent_app_number] => 075056 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3434438 [patent_doc_number] => 05463338 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-31 [patent_title] => 'Dual latch clocked LSSD and method' [patent_app_type] => 1 [patent_app_number] => 8/075363 [patent_app_country] => US [patent_app_date] => 1993-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4594 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/463/05463338.pdf [firstpage_image] =>[orig_patent_app_number] => 075363 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3462181 [patent_doc_number] => 05402083 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-28 [patent_title] => 'Shoot-through protection circuit for improved stability in a neutral-point clamped synthesizer' [patent_app_type] => 1 [patent_app_number] => 8/073027 [patent_app_country] => US [patent_app_date] => 1993-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1487 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 539 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/402/05402083.pdf [firstpage_image] =>[orig_patent_app_number] => 073027 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3485771 [patent_doc_number] => 05406134 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-11 [patent_title] => 'Bistable flip-flop with reset control' [patent_app_type] => 1 [patent_app_number] => 8/071078 [patent_app_country] => US [patent_app_date] => 1993-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2039 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/406/05406134.pdf [firstpage_image] =>[orig_patent_app_number] => 071078 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3428602 [patent_doc_number] => 05459422 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Edge selective delay circuit' [patent_app_type] => 1 [patent_app_number] => 8/070674 [patent_app_country] => US [patent_app_date] => 1993-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1659 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 454 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459422.pdf [firstpage_image] =>[orig_patent_app_number] => 070674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3003113 [patent_doc_number] => 05359236 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-25 [patent_title] => 'Integrated circuit thermal sensor' [patent_app_type] => 1 [patent_app_number] => 8/066854 [patent_app_country] => US [patent_app_date] => 1993-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3163 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/359/05359236.pdf [firstpage_image] =>[orig_patent_app_number] => 066854 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3121088 [patent_doc_number] => 05410269 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-04-25 [patent_title] => 'Sample-and-hold circuit' [patent_app_type] => 1 [patent_app_number] => 8/062753 [patent_app_country] => US [patent_app_date] => 1993-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3622 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/410/05410269.pdf [firstpage_image] =>[orig_patent_app_number] => 062753 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3081152 [patent_doc_number] => 05361289 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-01 [patent_title] => 'Synchronous counter circuit having a plurality of cascade-connected counters' [patent_app_type] => 1 [patent_app_number] => 8/061046 [patent_app_country] => US [patent_app_date] => 1993-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2946 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/361/05361289.pdf [firstpage_image] =>[orig_patent_app_number] => 061046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3429197 [patent_doc_number] => 05422593 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-06-06 [patent_title] => 'Current-limiting circuit' [patent_app_type] => 1 [patent_app_number] => 8/061172 [patent_app_country] => US [patent_app_date] => 1993-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 39 [patent_no_of_words] => 4755 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 309 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/422/05422593.pdf [firstpage_image] =>[orig_patent_app_number] => 061172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3447203 [patent_doc_number] => 05430393 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-07-04 [patent_title] => 'Integrated circuit with a low-power mode and clock amplifier circuit for same' [patent_app_type] => 1 [patent_app_number] => 8/058184 [patent_app_country] => US [patent_app_date] => 1993-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3395 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/430/05430393.pdf [firstpage_image] =>[orig_patent_app_number] => 058184 [rel_patent_id] =>[rel_patent_doc_number] =>)

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