| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3034881
[patent_doc_number] => 05343096
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-08-30
[patent_title] => 'System and method for tolerating dynamic circuit decay'
[patent_app_type] => 1
[patent_app_number] => 7/885584
[patent_app_country] => US
[patent_app_date] => 1992-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2526
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/343/05343096.pdf
[firstpage_image] =>[orig_patent_app_number] => 885584
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/885584 | System and method for tolerating dynamic circuit decay | May 18, 1992 | Issued |
Array
(
[id] => 3081171
[patent_doc_number] => 05361290
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-01
[patent_title] => 'Clock generating circuit for use in single chip microcomputer'
[patent_app_type] => 1
[patent_app_number] => 7/882222
[patent_app_country] => US
[patent_app_date] => 1992-05-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1939
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 492
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/361/05361290.pdf
[firstpage_image] =>[orig_patent_app_number] => 882222
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/882222 | Clock generating circuit for use in single chip microcomputer | May 12, 1992 | Issued |
Array
(
[id] => 2995441
[patent_doc_number] => 05347175
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-09-13
[patent_title] => 'Voltage comparator with reduced settling time'
[patent_app_type] => 1
[patent_app_number] => 7/882392
[patent_app_country] => US
[patent_app_date] => 1992-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 15
[patent_no_of_words] => 3501
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 195
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/347/05347175.pdf
[firstpage_image] =>[orig_patent_app_number] => 882392
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/882392 | Voltage comparator with reduced settling time | May 11, 1992 | Issued |
Array
(
[id] => 3491830
[patent_doc_number] => 05426386
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1995-06-20
[patent_title] => 'Low-power semiconductor voltage comparator with hysteresis'
[patent_app_type] => 1
[patent_app_number] => 7/871385
[patent_app_country] => US
[patent_app_date] => 1992-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4636
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 282
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/426/05426386.pdf
[firstpage_image] =>[orig_patent_app_number] => 871385
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/871385 | Low-power semiconductor voltage comparator with hysteresis | Apr 20, 1992 | Issued |
Array
(
[id] => 3080255
[patent_doc_number] => 05296752
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-22
[patent_title] => 'Current memory cell'
[patent_app_type] => 1
[patent_app_number] => 7/870657
[patent_app_country] => US
[patent_app_date] => 1992-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3290
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 199
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/296/05296752.pdf
[firstpage_image] =>[orig_patent_app_number] => 870657
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/870657 | Current memory cell | Apr 19, 1992 | Issued |
Array
(
[id] => 3097687
[patent_doc_number] => 05313113
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-17
[patent_title] => 'Sample and hold circuit with full signal modulation compensation using bipolar transistors of single conductivity type'
[patent_app_type] => 1
[patent_app_number] => 7/870369
[patent_app_country] => US
[patent_app_date] => 1992-04-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 6754
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/313/05313113.pdf
[firstpage_image] =>[orig_patent_app_number] => 870369
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/870369 | Sample and hold circuit with full signal modulation compensation using bipolar transistors of single conductivity type | Apr 16, 1992 | Issued |
Array
(
[id] => 3069274
[patent_doc_number] => 05311085
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-10
[patent_title] => 'Clocked comparator with offset-voltage compensation'
[patent_app_type] => 1
[patent_app_number] => 7/867594
[patent_app_country] => US
[patent_app_date] => 1992-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2452
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/311/05311085.pdf
[firstpage_image] =>[orig_patent_app_number] => 867594
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/867594 | Clocked comparator with offset-voltage compensation | Apr 12, 1992 | Issued |
Array
(
[id] => 3104358
[patent_doc_number] => 05315167
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-24
[patent_title] => 'Voltage burn-in scheme for BICMOS circuits'
[patent_app_type] => 1
[patent_app_number] => 7/865591
[patent_app_country] => US
[patent_app_date] => 1992-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3970
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/315/05315167.pdf
[firstpage_image] =>[orig_patent_app_number] => 865591
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/865591 | Voltage burn-in scheme for BICMOS circuits | Apr 8, 1992 | Issued |
Array
(
[id] => 2973937
[patent_doc_number] => 05258662
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-11-02
[patent_title] => 'Micropower gate charge pump for power MOSFETS'
[patent_app_type] => 1
[patent_app_number] => 7/862993
[patent_app_country] => US
[patent_app_date] => 1992-04-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 5476
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/258/05258662.pdf
[firstpage_image] =>[orig_patent_app_number] => 862993
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/862993 | Micropower gate charge pump for power MOSFETS | Apr 5, 1992 | Issued |
| 07/862128 | AUTOMATIC POLARITY SWITCHING OUTPUT CIRCUIT | Apr 1, 1992 | Abandoned |
Array
(
[id] => 3041018
[patent_doc_number] => 05317674
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-05-31
[patent_title] => 'Center-of-gravity determining circuit for pulse generation'
[patent_app_type] => 1
[patent_app_number] => 7/844309
[patent_app_country] => US
[patent_app_date] => 1992-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 7
[patent_no_of_words] => 1657
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/317/05317674.pdf
[firstpage_image] =>[orig_patent_app_number] => 844309
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/844309 | Center-of-gravity determining circuit for pulse generation | Mar 1, 1992 | Issued |
Array
(
[id] => 2967125
[patent_doc_number] => 05274273
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-12-28
[patent_title] => 'Method and apparatus for establishing a threshold with the use of a delay line'
[patent_app_type] => 1
[patent_app_number] => 7/830005
[patent_app_country] => US
[patent_app_date] => 1992-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 1861
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/274/05274273.pdf
[firstpage_image] =>[orig_patent_app_number] => 830005
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/830005 | Method and apparatus for establishing a threshold with the use of a delay line | Jan 30, 1992 | Issued |
Array
(
[id] => 3098260
[patent_doc_number] => 05369309
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-11-29
[patent_title] => 'Analog-to-digital converter and method of fabrication'
[patent_app_type] => 1
[patent_app_number] => 7/785325
[patent_app_country] => US
[patent_app_date] => 1991-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 88
[patent_figures_cnt] => 133
[patent_no_of_words] => 31837
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/369/05369309.pdf
[firstpage_image] =>[orig_patent_app_number] => 785325
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/785325 | Analog-to-digital converter and method of fabrication | Oct 29, 1991 | Issued |
Array
(
[id] => 3070332
[patent_doc_number] => 05294842
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1994-03-15
[patent_title] => 'Update synchronizer'
[patent_app_type] => 1
[patent_app_number] => 7/763795
[patent_app_country] => US
[patent_app_date] => 1991-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 5125
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/294/05294842.pdf
[firstpage_image] =>[orig_patent_app_number] => 763795
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/763795 | Update synchronizer | Sep 22, 1991 | Issued |
| 90/008848 | PARALLEL AND INTERWOVEN BUCK CONVERTER FOR HIGH EFFICIENCY, LOW VOLTAGE POWER SUPPLY | - | Pending |
| 90/019460 | APPARATUS, SYSTEMS, AND METHODS FOR NON-INVASIVE THERMAL INTERROGATION | - | Pending |
| 95/001996 | PAGING TRANSCEIVERS AND METHODS FOR SELECTIVELY RETRIEVING MESSAGES | - | Pending |
| 95/001135 | Electrical Adapter with Display Unit | - | Pending |
| 90/008490 | IMAGE CONTROLLERS WITH SHEET CONNECTED SENSORS | - | Pending |