Myron Wyche

Array ( [id] => 4191000 [patent_doc_number] => 06141630 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'System and method for automated design verification' [patent_app_type] => 1 [patent_app_number] => 8/908248 [patent_app_country] => US [patent_app_date] => 1997-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 6 [patent_no_of_words] => 4156 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 246 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/141/06141630.pdf [firstpage_image] =>[orig_patent_app_number] => 908248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4205884 [patent_doc_number] => 06086623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and implementation for intercepting and processing system calls in programmed digital computer to emulate retrograde operating system' [patent_app_type] => 1 [patent_app_number] => 8/885973 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3492 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/086/06086623.pdf [firstpage_image] =>[orig_patent_app_number] => 885973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4074528 [patent_doc_number] => 06053947 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Simulation model using object-oriented programming' [patent_app_type] => 1 [patent_app_number] => 8/866937 [patent_app_country] => US [patent_app_date] => 1997-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 13910 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/053/06053947.pdf [firstpage_image] =>[orig_patent_app_number] => 866937 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4230360 [patent_doc_number] => 06135627 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method, apparatus, and article of manufacture for modeling eddy current probes and simulating eddy current examinations' [patent_app_type] => 1 [patent_app_number] => 8/870424 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5209 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/135/06135627.pdf [firstpage_image] =>[orig_patent_app_number] => 870424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4222263 [patent_doc_number] => 06028996 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-22 [patent_title] => 'Method and apparatus for virtualizing system operation' [patent_app_type] => 1 [patent_app_number] => 8/819923 [patent_app_country] => US [patent_app_date] => 1997-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4896 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/028/06028996.pdf [firstpage_image] =>[orig_patent_app_number] => 819923 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4052705 [patent_doc_number] => 05995740 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Method for capturing ASIC I/O pin data for tester compatibility analysis' [patent_app_type] => 1 [patent_app_number] => 8/773469 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1989 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/995/05995740.pdf [firstpage_image] =>[orig_patent_app_number] => 773469 [rel_patent_id] =>[rel_patent_doc_number] =>)