Search

Nader Bolourchi

Examiner (ID: 12923, Phone: (571)272-8064 , Office: P/2631 )

Most Active Art Unit
2631
Art Unit(s)
2631, 2611
Total Applications
985
Issued Applications
780
Pending Applications
62
Abandoned Applications
154

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4577288 [patent_doc_number] => 07859354 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-12-28 [patent_title] => 'Ring oscillators' [patent_app_type] => utility [patent_app_number] => 11/960343 [patent_app_country] => US [patent_app_date] => 2007-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 34 [patent_no_of_words] => 7022 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859354.pdf [firstpage_image] =>[orig_patent_app_number] => 11960343 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/960343
Ring oscillators Dec 18, 2007 Issued
Array ( [id] => 4709929 [patent_doc_number] => 20080298455 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-12-04 [patent_title] => 'CLOCK GENERATOR INCLUDING A RING OSCILLATOR WITH PRECISE FREQUENCY CONTROL' [patent_app_type] => utility [patent_app_number] => 11/958053 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2697 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20080298455.pdf [firstpage_image] =>[orig_patent_app_number] => 11958053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958053
CLOCK GENERATOR INCLUDING A RING OSCILLATOR WITH PRECISE FREQUENCY CONTROL Dec 16, 2007 Abandoned
Array ( [id] => 5543376 [patent_doc_number] => 20090153253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING LOCK TIME IN A PHASE-LOCKED LOOP' [patent_app_type] => utility [patent_app_number] => 11/958189 [patent_app_country] => US [patent_app_date] => 2007-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2988 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20090153253.pdf [firstpage_image] =>[orig_patent_app_number] => 11958189 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/958189
System and method for reducing lock time in a phase-locked loop Dec 16, 2007 Issued
Array ( [id] => 6344254 [patent_doc_number] => 20100085122 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'DEVICE WITH TWO DIFFERENTIAL OSCILLATORS WITH PULSED POWER SUPPLY COUPLED TO AND IN QUADRATURE-PHASE WITH EACH OTHER' [patent_app_type] => utility [patent_app_number] => 12/518811 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8082 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085122.pdf [firstpage_image] =>[orig_patent_app_number] => 12518811 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/518811
Device with two differential oscillators with pulsed power supply coupled to and in quadrature-phase with each other Dec 10, 2007 Issued
Array ( [id] => 5506299 [patent_doc_number] => 20090079506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-26 [patent_title] => 'PHASE-LOCKED LOOP AND METHOD WITH FREQUENCY CALIBRATION' [patent_app_type] => utility [patent_app_number] => 11/950186 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20090079506.pdf [firstpage_image] =>[orig_patent_app_number] => 11950186 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/950186
PHASE-LOCKED LOOP AND METHOD WITH FREQUENCY CALIBRATION Dec 3, 2007 Abandoned
Array ( [id] => 5320545 [patent_doc_number] => 20090058535 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'CONSTANT CALIBRATION' [patent_app_type] => utility [patent_app_number] => 11/947730 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9492 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20090058535.pdf [firstpage_image] =>[orig_patent_app_number] => 11947730 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947730
Constant calibration Nov 28, 2007 Issued
Array ( [id] => 5613 [patent_doc_number] => 07816993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Temperature compensated crystal oscillator' [patent_app_type] => utility [patent_app_number] => 11/984970 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2722 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816993.pdf [firstpage_image] =>[orig_patent_app_number] => 11984970 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984970
Temperature compensated crystal oscillator Nov 25, 2007 Issued
Array ( [id] => 45654 [patent_doc_number] => 07777581 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Voltage Controlled Oscillator (VCO) with a wide tuning range and substantially constant voltage swing over the tuning range' [patent_app_type] => utility [patent_app_number] => 11/984852 [patent_app_country] => US [patent_app_date] => 2007-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7894 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777581.pdf [firstpage_image] =>[orig_patent_app_number] => 11984852 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984852
Voltage Controlled Oscillator (VCO) with a wide tuning range and substantially constant voltage swing over the tuning range Nov 22, 2007 Issued
Array ( [id] => 124629 [patent_doc_number] => 07705686 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-27 [patent_title] => 'Injection-locked frequency divider' [patent_app_type] => utility [patent_app_number] => 11/984696 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3708 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 406 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/705/07705686.pdf [firstpage_image] =>[orig_patent_app_number] => 11984696 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984696
Injection-locked frequency divider Nov 20, 2007 Issued
Array ( [id] => 5276074 [patent_doc_number] => 20090128206 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler' [patent_app_type] => utility [patent_app_number] => 11/942983 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6906 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20090128206.pdf [firstpage_image] =>[orig_patent_app_number] => 11942983 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942983
Apparatus and Method for Obtaining Desired Phase Locked Loop Duty Cycle without Pre-Scaler Nov 19, 2007 Abandoned
Array ( [id] => 4540040 [patent_doc_number] => 07889014 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-02-15 [patent_title] => 'Ring based impedance control of an output driver' [patent_app_type] => utility [patent_app_number] => 11/986337 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 11361 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889014.pdf [firstpage_image] =>[orig_patent_app_number] => 11986337 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986337
Ring based impedance control of an output driver Nov 19, 2007 Issued
Array ( [id] => 4821552 [patent_doc_number] => 20080122548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-05-29 [patent_title] => 'OSCILLATOR USING SCHMITT TRIGGER CIRCUIT' [patent_app_type] => utility [patent_app_number] => 11/942530 [patent_app_country] => US [patent_app_date] => 2007-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5365 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20080122548.pdf [firstpage_image] =>[orig_patent_app_number] => 11942530 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/942530
OSCILLATOR USING SCHMITT TRIGGER CIRCUIT Nov 18, 2007 Abandoned
Array ( [id] => 7531050 [patent_doc_number] => 07843275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-30 [patent_title] => 'Frequency synthesizer circuitry employing delay line' [patent_app_type] => utility [patent_app_number] => 11/975457 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1506 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/843/07843275.pdf [firstpage_image] =>[orig_patent_app_number] => 11975457 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/975457
Frequency synthesizer circuitry employing delay line Oct 18, 2007 Issued
Array ( [id] => 5583366 [patent_doc_number] => 20090102568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-23 [patent_title] => 'VOLTAGE CONTROLLED OSCILLATOR WITH CASCADED EMITTER FOLLOWER BUFFER STAGES' [patent_app_type] => utility [patent_app_number] => 11/873793 [patent_app_country] => US [patent_app_date] => 2007-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0102/20090102568.pdf [firstpage_image] =>[orig_patent_app_number] => 11873793 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/873793
Voltage controlled oscillator with cascaded emitter follower buffer stages Oct 16, 2007 Issued
Array ( [id] => 5426365 [patent_doc_number] => 20090085675 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH UNDERSAMPLED FEEDBACK' [patent_app_type] => utility [patent_app_number] => 11/864843 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4630 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085675.pdf [firstpage_image] =>[orig_patent_app_number] => 11864843 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864843
Method and system for signal generation via a PLL with undersampled feedback Sep 27, 2007 Issued
Array ( [id] => 5426368 [patent_doc_number] => 20090085678 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A DIGITALLY CONTROLLED OSCILLATOR' [patent_app_type] => utility [patent_app_number] => 11/864839 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4976 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085678.pdf [firstpage_image] =>[orig_patent_app_number] => 11864839 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864839
METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A DIGITALLY CONTROLLED OSCILLATOR Sep 27, 2007 Abandoned
Array ( [id] => 5426364 [patent_doc_number] => 20090085674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-02 [patent_title] => 'METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DIGITAL PHASE DETECTION' [patent_app_type] => utility [patent_app_number] => 11/863871 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4351 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20090085674.pdf [firstpage_image] =>[orig_patent_app_number] => 11863871 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863871
METHOD AND SYSTEM FOR SIGNAL GENERATION VIA A PLL WITH DIGITAL PHASE DETECTION Sep 27, 2007 Abandoned
Array ( [id] => 191547 [patent_doc_number] => 07642861 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-05 [patent_title] => 'Locked loop system' [patent_app_type] => utility [patent_app_number] => 11/863126 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3838 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/642/07642861.pdf [firstpage_image] =>[orig_patent_app_number] => 11863126 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/863126
Locked loop system Sep 26, 2007 Issued
Array ( [id] => 7968661 [patent_doc_number] => 07940132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Clock system and applications thereof' [patent_app_type] => utility [patent_app_number] => 11/862312 [patent_app_country] => US [patent_app_date] => 2007-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3666 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/940/07940132.pdf [firstpage_image] =>[orig_patent_app_number] => 11862312 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/862312
Clock system and applications thereof Sep 26, 2007 Issued
Array ( [id] => 4936894 [patent_doc_number] => 20080074208 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-27 [patent_title] => 'DEVICE AND METHOD OF TWO-POINT MODULATION' [patent_app_type] => utility [patent_app_number] => 11/856452 [patent_app_country] => US [patent_app_date] => 2007-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3052 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20080074208.pdf [firstpage_image] =>[orig_patent_app_number] => 11856452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/856452
DEVICE AND METHOD OF TWO-POINT MODULATION Sep 16, 2007 Abandoned
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