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Nam Thanh Nguyen

Examiner (ID: 741)

Most Active Art Unit
2824
Art Unit(s)
2824, CSDE
Total Applications
700
Issued Applications
674
Pending Applications
6
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 10871852 [patent_doc_number] => 08897065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Efficient data storage in multi-plane memory devices' [patent_app_type] => utility [patent_app_number] => 14/257268 [patent_app_country] => US [patent_app_date] => 2014-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8410 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14257268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/257268
Efficient data storage in multi-plane memory devices Apr 20, 2014 Issued
Array ( [id] => 9712656 [patent_doc_number] => 08837242 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-09-16 [patent_title] => 'Semiconductor device and method including redundant bit line provided to replace defective bit line' [patent_app_type] => utility [patent_app_number] => 14/163368 [patent_app_country] => US [patent_app_date] => 2014-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5183 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14163368 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/163368
Semiconductor device and method including redundant bit line provided to replace defective bit line Jan 23, 2014 Issued
Array ( [id] => 9819352 [patent_doc_number] => 08929147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-01-06 [patent_title] => 'Determining threshold voltage distribution in flash memory' [patent_app_type] => utility [patent_app_number] => 14/139552 [patent_app_country] => US [patent_app_date] => 2013-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14139552 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/139552
Determining threshold voltage distribution in flash memory Dec 22, 2013 Issued
Array ( [id] => 9819331 [patent_doc_number] => 08929126 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-01-06 [patent_title] => 'Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements' [patent_app_type] => utility [patent_app_number] => 14/024946 [patent_app_country] => US [patent_app_date] => 2013-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 36 [patent_no_of_words] => 19586 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14024946 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/024946
Array voltage regulating technique to enable data operations on large cross-point memory arrays with resistive memory elements Sep 11, 2013 Issued
Array ( [id] => 9180178 [patent_doc_number] => 20130322163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-12-05 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/963955 [patent_app_country] => US [patent_app_date] => 2013-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6013 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13963955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/963955
Semiconductor memory device Aug 8, 2013 Issued
Array ( [id] => 9505302 [patent_doc_number] => 08743625 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-03 [patent_title] => 'Semiconductor integrated circuit adapted to output pass/fail results of internal operations' [patent_app_type] => utility [patent_app_number] => 13/901093 [patent_app_country] => US [patent_app_date] => 2013-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 35 [patent_figures_cnt] => 71 [patent_no_of_words] => 10451 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13901093 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/901093
Semiconductor integrated circuit adapted to output pass/fail results of internal operations May 22, 2013 Issued
Array ( [id] => 9525773 [patent_doc_number] => 08750057 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-06-10 [patent_title] => 'Memory devices and methods of operating memory' [patent_app_type] => utility [patent_app_number] => 13/891832 [patent_app_country] => US [patent_app_date] => 2013-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 4104 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891832 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891832
Memory devices and methods of operating memory May 9, 2013 Issued
Array ( [id] => 9056756 [patent_doc_number] => 20130254470 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'EFFICIENT DATA STORAGE IN MULTI-PLANE MEMORY DEVICES' [patent_app_type] => utility [patent_app_number] => 13/890704 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8392 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13890704 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/890704
Efficient data storage in multi-plane memory devices May 8, 2013 Issued
Array ( [id] => 9429219 [patent_doc_number] => 08705301 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-22 [patent_title] => 'System and method for controlling timing of output signals' [patent_app_type] => utility [patent_app_number] => 13/855553 [patent_app_country] => US [patent_app_date] => 2013-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4623 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13855553 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/855553
System and method for controlling timing of output signals Apr 1, 2013 Issued
Array ( [id] => 9456794 [patent_doc_number] => 08717811 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Latching circuit' [patent_app_type] => utility [patent_app_number] => 13/785338 [patent_app_country] => US [patent_app_date] => 2013-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10048 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13785338 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/785338
Latching circuit Mar 4, 2013 Issued
Array ( [id] => 8915154 [patent_doc_number] => 20130176779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-07-11 [patent_title] => 'INTER-CELL INTERFERENCE CANCELLATION IN FLASH MEMORIES' [patent_app_type] => utility [patent_app_number] => 13/778860 [patent_app_country] => US [patent_app_date] => 2013-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7052 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13778860 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/778860
Inter-cell interference cancellation in flash memories Feb 26, 2013 Issued
Array ( [id] => 8975101 [patent_doc_number] => 20130208531 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-08-15 [patent_title] => 'NONVOLATILE MEMORY DEVICE AND METHOD OF WRITING DATA TO NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/774816 [patent_app_country] => US [patent_app_date] => 2013-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 40 [patent_no_of_words] => 35776 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13774816 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/774816
Nonvolatile memory device and method of writing data to nonvolatile memory device Feb 21, 2013 Issued
Array ( [id] => 9301004 [patent_doc_number] => 08649240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-11 [patent_title] => 'Mechanism for peak power management in a memory' [patent_app_type] => utility [patent_app_number] => 13/769542 [patent_app_country] => US [patent_app_date] => 2013-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3742 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13769542 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/769542
Mechanism for peak power management in a memory Feb 17, 2013 Issued
Array ( [id] => 9101126 [patent_doc_number] => 08565015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-22 [patent_title] => 'Methods of programming two terminal memory cells' [patent_app_type] => utility [patent_app_number] => 13/765394 [patent_app_country] => US [patent_app_date] => 2013-02-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 3739 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13765394 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/765394
Methods of programming two terminal memory cells Feb 11, 2013 Issued
Array ( [id] => 8852305 [patent_doc_number] => 20130141980 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-06 [patent_title] => 'REDUCED SIGNAL INTERFACE MEMORY DEVICE, SYSTEM, AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/758627 [patent_app_country] => US [patent_app_date] => 2013-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3829 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13758627 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/758627
Reduced signal interface memory device, system, and method Feb 3, 2013 Issued
Array ( [id] => 8882586 [patent_doc_number] => 20130155770 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-20 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 13/714953 [patent_app_country] => US [patent_app_date] => 2012-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16122 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13714953 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/714953
Semiconductor memory device Dec 13, 2012 Issued
Array ( [id] => 9185423 [patent_doc_number] => 08625369 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-01-07 [patent_title] => 'Determining threshold voltage distribution in flash memory' [patent_app_type] => utility [patent_app_number] => 13/690371 [patent_app_country] => US [patent_app_date] => 2012-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6329 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13690371 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/690371
Determining threshold voltage distribution in flash memory Nov 29, 2012 Issued
Array ( [id] => 10846105 [patent_doc_number] => 08873295 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-28 [patent_title] => 'Memory and operation method thereof' [patent_app_type] => utility [patent_app_number] => 13/685719 [patent_app_country] => US [patent_app_date] => 2012-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13685719 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/685719
Memory and operation method thereof Nov 26, 2012 Issued
Array ( [id] => 9155108 [patent_doc_number] => 08588018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Integrated solution for identifying malfunctioning components within memory devices' [patent_app_type] => utility [patent_app_number] => 13/684992 [patent_app_country] => US [patent_app_date] => 2012-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6854 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13684992 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/684992
Integrated solution for identifying malfunctioning components within memory devices Nov 25, 2012 Issued
Array ( [id] => 10859190 [patent_doc_number] => 08885397 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-11 [patent_title] => 'Self-referenced MRAM cell with optimized reliability' [patent_app_type] => utility [patent_app_number] => 13/683239 [patent_app_country] => US [patent_app_date] => 2012-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2539 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13683239 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/683239
Self-referenced MRAM cell with optimized reliability Nov 20, 2012 Issued
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