Search

Nam Thanh Nguyen

Examiner (ID: 15670)

Most Active Art Unit
2824
Art Unit(s)
CSDE, 2824
Total Applications
700
Issued Applications
674
Pending Applications
6
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6298537 [patent_doc_number] => 20100067308 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-18 [patent_title] => 'Sub Volt Flash Memory System' [patent_app_type] => utility [patent_app_number] => 12/623306 [patent_app_country] => US [patent_app_date] => 2009-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9637 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20100067308.pdf [firstpage_image] =>[orig_patent_app_number] => 12623306 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/623306
Sub volt flash memory system Nov 19, 2009 Issued
Array ( [id] => 7999349 [patent_doc_number] => 08081522 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-20 [patent_title] => 'Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method' [patent_app_type] => utility [patent_app_number] => 12/613993 [patent_app_country] => US [patent_app_date] => 2009-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 6541 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/081/08081522.pdf [firstpage_image] =>[orig_patent_app_number] => 12613993 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/613993
Page buffer circuit for electrically rewritable non-volatile semiconductor memory device and control method Nov 5, 2009 Issued
Array ( [id] => 6276624 [patent_doc_number] => 20100118592 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF CONTROLLING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/611279 [patent_app_country] => US [patent_app_date] => 2009-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 15743 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20100118592.pdf [firstpage_image] =>[orig_patent_app_number] => 12611279 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/611279
Nonvolatile semiconductor memory device and method of controlling the same Nov 2, 2009 Issued
Array ( [id] => 6023166 [patent_doc_number] => 20110051492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'RESISTANCE CHANGE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/605799 [patent_app_country] => US [patent_app_date] => 2009-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 16259 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20110051492.pdf [firstpage_image] =>[orig_patent_app_number] => 12605799 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/605799
Resistance change memory device Oct 25, 2009 Issued
Array ( [id] => 6588916 [patent_doc_number] => 20100097832 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'NONVOLATILE SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/580795 [patent_app_country] => US [patent_app_date] => 2009-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5390 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097832.pdf [firstpage_image] =>[orig_patent_app_number] => 12580795 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/580795
Nonvolatile semiconductor memory device Oct 15, 2009 Issued
Array ( [id] => 6123419 [patent_doc_number] => 20110085378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'Memory and Operation Method Therefor' [patent_app_type] => utility [patent_app_number] => 12/576323 [patent_app_country] => US [patent_app_date] => 2009-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5275 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20110085378.pdf [firstpage_image] =>[orig_patent_app_number] => 12576323 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/576323
Memory and operation method therefor Oct 8, 2009 Issued
Array ( [id] => 6029421 [patent_doc_number] => 20110080784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-07 [patent_title] => 'NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/574093 [patent_app_country] => US [patent_app_date] => 2009-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5094 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0080/20110080784.pdf [firstpage_image] =>[orig_patent_app_number] => 12574093 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/574093
Non-volatile memory and operation method thereof Oct 5, 2009 Issued
Array ( [id] => 7754118 [patent_doc_number] => 08111565 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Memory interface and operation method of it' [patent_app_type] => utility [patent_app_number] => 12/569383 [patent_app_country] => US [patent_app_date] => 2009-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5761 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/111/08111565.pdf [firstpage_image] =>[orig_patent_app_number] => 12569383 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/569383
Memory interface and operation method of it Sep 28, 2009 Issued
Array ( [id] => 6470390 [patent_doc_number] => 20100091575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-15 [patent_title] => 'PROGRAMMING METHOD AND INITIAL CHARGING METHOD OF NONVOLATILE MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/567819 [patent_app_country] => US [patent_app_date] => 2009-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 4858 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20100091575.pdf [firstpage_image] =>[orig_patent_app_number] => 12567819 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/567819
Programming method and initial charging method of nonvolatile memory device Sep 27, 2009 Issued
Array ( [id] => 5974527 [patent_doc_number] => 20110069566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-24 [patent_title] => 'MEMORY CELL WRITE' [patent_app_type] => utility [patent_app_number] => 12/564765 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5872 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20110069566.pdf [firstpage_image] =>[orig_patent_app_number] => 12564765 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564765
Memory cell write Sep 21, 2009 Issued
Array ( [id] => 6361544 [patent_doc_number] => 20100074039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-25 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR TESTING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/564183 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6473 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20100074039.pdf [firstpage_image] =>[orig_patent_app_number] => 12564183 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564183
Semiconductor memory device and method for testing the same Sep 21, 2009 Issued
Array ( [id] => 4515327 [patent_doc_number] => 07916563 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-29 [patent_title] => 'Programmable control block for dual port SRAM application' [patent_app_type] => utility [patent_app_number] => 12/564368 [patent_app_country] => US [patent_app_date] => 2009-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 6393 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/916/07916563.pdf [firstpage_image] =>[orig_patent_app_number] => 12564368 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/564368
Programmable control block for dual port SRAM application Sep 21, 2009 Issued
Array ( [id] => 8234103 [patent_doc_number] => 08199561 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Phase change memory' [patent_app_type] => utility [patent_app_number] => 12/563971 [patent_app_country] => US [patent_app_date] => 2009-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2579 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/199/08199561.pdf [firstpage_image] =>[orig_patent_app_number] => 12563971 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563971
Phase change memory Sep 20, 2009 Issued
Array ( [id] => 6484123 [patent_doc_number] => 20100208541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'CACHE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/563145 [patent_app_country] => US [patent_app_date] => 2009-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5818 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0208/20100208541.pdf [firstpage_image] =>[orig_patent_app_number] => 12563145 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/563145
Cache memory Sep 19, 2009 Issued
Array ( [id] => 7777231 [patent_doc_number] => 08120942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/559931 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3295 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/120/08120942.pdf [firstpage_image] =>[orig_patent_app_number] => 12559931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559931
Semiconductor memory device Sep 14, 2009 Issued
Array ( [id] => 4491848 [patent_doc_number] => 07903476 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Systems and techniques for non-volatile memory buffering' [patent_app_type] => utility [patent_app_number] => 12/559761 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8139 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/903/07903476.pdf [firstpage_image] =>[orig_patent_app_number] => 12559761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/559761
Systems and techniques for non-volatile memory buffering Sep 14, 2009 Issued
Array ( [id] => 6201111 [patent_doc_number] => 20110063897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'DIFFERENTIAL READ AND WRITE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/558451 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063897.pdf [firstpage_image] =>[orig_patent_app_number] => 12558451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558451
Differential read and write architecture Sep 10, 2009 Issued
Array ( [id] => 7990433 [patent_doc_number] => 08077520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Determining threshold voltage distribution in flash memory' [patent_app_type] => utility [patent_app_number] => 12/552925 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6368 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/077/08077520.pdf [firstpage_image] =>[orig_patent_app_number] => 12552925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552925
Determining threshold voltage distribution in flash memory Sep 1, 2009 Issued
Array ( [id] => 5372863 [patent_doc_number] => 20090310423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'METHOD OF PROGRAMMING AND ERASING A NON-VOLATILE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/543830 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3993 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20090310423.pdf [firstpage_image] =>[orig_patent_app_number] => 12543830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543830
Method of programming and erasing a non-volatile memory array Aug 18, 2009 Issued
Array ( [id] => 4544417 [patent_doc_number] => 07889560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Alternate row-based reading and writing for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/538773 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 19624 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889560.pdf [firstpage_image] =>[orig_patent_app_number] => 12538773 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538773
Alternate row-based reading and writing for non-volatile memory Aug 9, 2009 Issued
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