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Nam Thanh Nguyen

Examiner (ID: 741)

Most Active Art Unit
2824
Art Unit(s)
2824, CSDE
Total Applications
700
Issued Applications
674
Pending Applications
6
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6201111 [patent_doc_number] => 20110063897 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'DIFFERENTIAL READ AND WRITE ARCHITECTURE' [patent_app_type] => utility [patent_app_number] => 12/558451 [patent_app_country] => US [patent_app_date] => 2009-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5341 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20110063897.pdf [firstpage_image] =>[orig_patent_app_number] => 12558451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/558451
Differential read and write architecture Sep 10, 2009 Issued
Array ( [id] => 7990433 [patent_doc_number] => 08077520 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-12-13 [patent_title] => 'Determining threshold voltage distribution in flash memory' [patent_app_type] => utility [patent_app_number] => 12/552925 [patent_app_country] => US [patent_app_date] => 2009-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6368 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/077/08077520.pdf [firstpage_image] =>[orig_patent_app_number] => 12552925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/552925
Determining threshold voltage distribution in flash memory Sep 1, 2009 Issued
Array ( [id] => 5372863 [patent_doc_number] => 20090310423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'METHOD OF PROGRAMMING AND ERASING A NON-VOLATILE MEMORY ARRAY' [patent_app_type] => utility [patent_app_number] => 12/543830 [patent_app_country] => US [patent_app_date] => 2009-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 3993 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20090310423.pdf [firstpage_image] =>[orig_patent_app_number] => 12543830 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/543830
Method of programming and erasing a non-volatile memory array Aug 18, 2009 Issued
Array ( [id] => 4544417 [patent_doc_number] => 07889560 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Alternate row-based reading and writing for non-volatile memory' [patent_app_type] => utility [patent_app_number] => 12/538773 [patent_app_country] => US [patent_app_date] => 2009-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 27 [patent_no_of_words] => 19624 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/889/07889560.pdf [firstpage_image] =>[orig_patent_app_number] => 12538773 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/538773
Alternate row-based reading and writing for non-volatile memory Aug 9, 2009 Issued
Array ( [id] => 4559642 [patent_doc_number] => 07961501 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-06-14 [patent_title] => 'Radiation sensors and single-event-effects suppression devices' [patent_app_type] => utility [patent_app_number] => 12/537958 [patent_app_country] => US [patent_app_date] => 2009-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 9345 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/961/07961501.pdf [firstpage_image] =>[orig_patent_app_number] => 12537958 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/537958
Radiation sensors and single-event-effects suppression devices Aug 6, 2009 Issued
Array ( [id] => 6565035 [patent_doc_number] => 20100046292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-02-25 [patent_title] => 'Non-volatile memory device and bad block remapping method' [patent_app_type] => utility [patent_app_number] => 12/458999 [patent_app_country] => US [patent_app_date] => 2009-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3843 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20100046292.pdf [firstpage_image] =>[orig_patent_app_number] => 12458999 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/458999
Non-volatile memory device and bad block remapping method Jul 28, 2009 Issued
Array ( [id] => 4640728 [patent_doc_number] => 08018758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-09-13 [patent_title] => 'Gate drive voltage boost schemes for memory array' [patent_app_type] => utility [patent_app_number] => 12/459655 [patent_app_country] => US [patent_app_date] => 2009-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3593 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/018/08018758.pdf [firstpage_image] =>[orig_patent_app_number] => 12459655 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/459655
Gate drive voltage boost schemes for memory array Jul 5, 2009 Issued
Array ( [id] => 6243260 [patent_doc_number] => 20100135098 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'Power control circuit and semiconductor memory device using the same' [patent_app_type] => utility [patent_app_number] => 12/459345 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3806 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20100135098.pdf [firstpage_image] =>[orig_patent_app_number] => 12459345 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/459345
Power control circuit and semiconductor memory device using the same Jun 29, 2009 Issued
Array ( [id] => 7732283 [patent_doc_number] => 08102722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-01-24 [patent_title] => 'Data output device for semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/494377 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4506 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102722.pdf [firstpage_image] =>[orig_patent_app_number] => 12494377 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/494377
Data output device for semiconductor memory apparatus Jun 29, 2009 Issued
Array ( [id] => 7528796 [patent_doc_number] => 08045400 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Circuit and method for controlling read cycle' [patent_app_type] => utility [patent_app_number] => 12/495269 [patent_app_country] => US [patent_app_date] => 2009-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2590 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/045/08045400.pdf [firstpage_image] =>[orig_patent_app_number] => 12495269 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/495269
Circuit and method for controlling read cycle Jun 29, 2009 Issued
Array ( [id] => 6337453 [patent_doc_number] => 20100329004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'DETECTING THE COMPLETION OF PROGRAMMING FOR NON-VOLATILE STORAGE' [patent_app_type] => utility [patent_app_number] => 12/492421 [patent_app_country] => US [patent_app_date] => 2009-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17086 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0329/20100329004.pdf [firstpage_image] =>[orig_patent_app_number] => 12492421 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/492421
Detecting the completion of programming for non-volatile storage Jun 25, 2009 Issued
Array ( [id] => 6348455 [patent_doc_number] => 20100085797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'DUAL STAGE SENSING FOR NON-VOLATILE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/490493 [patent_app_country] => US [patent_app_date] => 2009-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3781 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085797.pdf [firstpage_image] =>[orig_patent_app_number] => 12490493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/490493
Dual stage sensing for non-volatile memory Jun 23, 2009 Issued
Array ( [id] => 6588648 [patent_doc_number] => 20100322027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-23 [patent_title] => 'MEMORY USING MULTIPLE SUPPLY VOLTAGES' [patent_app_type] => utility [patent_app_number] => 12/487791 [patent_app_country] => US [patent_app_date] => 2009-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4857 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0322/20100322027.pdf [firstpage_image] =>[orig_patent_app_number] => 12487791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/487791
Memory using multiple supply voltages Jun 18, 2009 Issued
Array ( [id] => 7528808 [patent_doc_number] => 08045412 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-10-25 [patent_title] => 'Multi-stage parallel data transfer' [patent_app_type] => utility [patent_app_number] => 12/487165 [patent_app_country] => US [patent_app_date] => 2009-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3810 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/045/08045412.pdf [firstpage_image] =>[orig_patent_app_number] => 12487165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/487165
Multi-stage parallel data transfer Jun 17, 2009 Issued
Array ( [id] => 6374696 [patent_doc_number] => 20100315856 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-16 [patent_title] => 'HIGH-DENSITY NON-VOLATILE READ-ONLY MEMORY ARRAYS AND RELATED METHODS' [patent_app_type] => utility [patent_app_number] => 12/485749 [patent_app_country] => US [patent_app_date] => 2009-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7496 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0315/20100315856.pdf [firstpage_image] =>[orig_patent_app_number] => 12485749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/485749
High-density non-volatile read-only memory arrays and related methods Jun 15, 2009 Issued
Array ( [id] => 4500933 [patent_doc_number] => 07957218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Memory controller with skew control and method' [patent_app_type] => utility [patent_app_number] => 12/482509 [patent_app_country] => US [patent_app_date] => 2009-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4354 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/957/07957218.pdf [firstpage_image] =>[orig_patent_app_number] => 12482509 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/482509
Memory controller with skew control and method Jun 10, 2009 Issued
Array ( [id] => 6602506 [patent_doc_number] => 20100309710 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'Variable Impedance Circuit Controlled by a Ferroelectric Capacitor' [patent_app_type] => utility [patent_app_number] => 12/480645 [patent_app_country] => US [patent_app_date] => 2009-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5256 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0309/20100309710.pdf [firstpage_image] =>[orig_patent_app_number] => 12480645 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/480645
Variable impedance circuit controlled by a ferroelectric capacitor Jun 7, 2009 Issued
Array ( [id] => 5372862 [patent_doc_number] => 20090310422 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-17 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 12/478181 [patent_app_country] => US [patent_app_date] => 2009-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6251 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0310/20090310422.pdf [firstpage_image] =>[orig_patent_app_number] => 12478181 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/478181
Non-volatile semiconductor storage device Jun 3, 2009 Issued
Array ( [id] => 8030899 [patent_doc_number] => 08144541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-27 [patent_title] => 'Method and apparatus for adjusting and obtaining a reference voltage' [patent_app_type] => utility [patent_app_number] => 12/666771 [patent_app_country] => US [patent_app_date] => 2009-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3632 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/144/08144541.pdf [firstpage_image] =>[orig_patent_app_number] => 12666771 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/666771
Method and apparatus for adjusting and obtaining a reference voltage May 24, 2009 Issued
Array ( [id] => 6465218 [patent_doc_number] => 20100281477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'VM HOST RESPONDING TO INITIATION OF A PAGE SWAP BY TRANSFERRING PAGES FROM HOST-BUT-NON-GUEST-ADDRESSABLE RAM TO HOST-AND-GUEST-ADDRESSABLE RAM' [patent_app_type] => utility [patent_app_number] => 12/432770 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2604 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0281/20100281477.pdf [firstpage_image] =>[orig_patent_app_number] => 12432770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432770
VM host responding to initiation of a page swap by transferring pages from host-but-non-guest-addressable RAM to host-and-guest-addressable RAM Apr 29, 2009 Issued
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