
Nam Thanh Nguyen
Examiner (ID: 741)
| Most Active Art Unit | 2824 |
| Art Unit(s) | 2824, CSDE |
| Total Applications | 700 |
| Issued Applications | 674 |
| Pending Applications | 6 |
| Abandoned Applications | 24 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 5491794
[patent_doc_number] => 20090292865
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-11-26
[patent_title] => 'SYSTEMS AND METHODS FOR SCHEDULING A MEMORY COMMAND FOR EXECUTION BASED ON A HISTORY OF PREVIOUSLY EXECUTED MEMORY COMMANDS'
[patent_app_type] => utility
[patent_app_number] => 12/432299
[patent_app_country] => US
[patent_app_date] => 2009-04-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 5193
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0292/20090292865.pdf
[firstpage_image] =>[orig_patent_app_number] => 12432299
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/432299 | Systems and methods for scheduling a memory command for execution based on a history of previously executed memory commands | Apr 28, 2009 | Issued |
Array
(
[id] => 7803686
[patent_doc_number] => 08131970
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-03-06
[patent_title] => 'Compiler based cache allocation'
[patent_app_type] => utility
[patent_app_number] => 12/427609
[patent_app_country] => US
[patent_app_date] => 2009-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5951
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 76
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/131/08131970.pdf
[firstpage_image] =>[orig_patent_app_number] => 12427609
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/427609 | Compiler based cache allocation | Apr 20, 2009 | Issued |
Array
(
[id] => 7706191
[patent_doc_number] => 08090911
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2012-01-03
[patent_title] => 'Selecting a target number of pages for allocation to a partition'
[patent_app_type] => utility
[patent_app_number] => 12/424772
[patent_app_country] => US
[patent_app_date] => 2009-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 11761
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 204
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/090/08090911.pdf
[firstpage_image] =>[orig_patent_app_number] => 12424772
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/424772 | Selecting a target number of pages for allocation to a partition | Apr 15, 2009 | Issued |
Array
(
[id] => 7992979
[patent_doc_number] => 08078796
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-13
[patent_title] => 'Method for writing to and erasing a non-volatile memory'
[patent_app_type] => utility
[patent_app_number] => 12/423226
[patent_app_country] => US
[patent_app_date] => 2009-04-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5401
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/078/08078796.pdf
[firstpage_image] =>[orig_patent_app_number] => 12423226
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/423226 | Method for writing to and erasing a non-volatile memory | Apr 13, 2009 | Issued |
Array
(
[id] => 4491842
[patent_doc_number] => 07903475
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-03-08
[patent_title] => 'Latch pulse delay control'
[patent_app_type] => utility
[patent_app_number] => 12/416433
[patent_app_country] => US
[patent_app_date] => 2009-04-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 5617
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 85
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/903/07903475.pdf
[firstpage_image] =>[orig_patent_app_number] => 12416433
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/416433 | Latch pulse delay control | Mar 31, 2009 | Issued |
Array
(
[id] => 5354098
[patent_doc_number] => 20090185442
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-07-23
[patent_title] => 'MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES'
[patent_app_type] => utility
[patent_app_number] => 12/412968
[patent_app_country] => US
[patent_app_date] => 2009-03-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 7031
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0185/20090185442.pdf
[firstpage_image] =>[orig_patent_app_number] => 12412968
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/412968 | Memory system and method with serial and parallel modes | Mar 26, 2009 | Issued |
Array
(
[id] => 35044
[patent_doc_number] => 07791961
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-09-07
[patent_title] => 'Semiconductor device and method for boosting word line'
[patent_app_type] => utility
[patent_app_number] => 12/406845
[patent_app_country] => US
[patent_app_date] => 2009-03-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 17
[patent_no_of_words] => 10553
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/791/07791961.pdf
[firstpage_image] =>[orig_patent_app_number] => 12406845
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/406845 | Semiconductor device and method for boosting word line | Mar 17, 2009 | Issued |
Array
(
[id] => 5396408
[patent_doc_number] => 20090316471
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-12-24
[patent_title] => 'RESISTANCE CHANGE MEMORY'
[patent_app_type] => utility
[patent_app_number] => 12/404115
[patent_app_country] => US
[patent_app_date] => 2009-03-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 6679
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0316/20090316471.pdf
[firstpage_image] =>[orig_patent_app_number] => 12404115
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/404115 | Resistance change memory | Mar 12, 2009 | Issued |
Array
(
[id] => 5384365
[patent_doc_number] => 20090225609
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-10
[patent_title] => 'SEMICONDUCTOR MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/402151
[patent_app_country] => US
[patent_app_date] => 2009-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 20152
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0225/20090225609.pdf
[firstpage_image] =>[orig_patent_app_number] => 12402151
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/402151 | Semiconductor memory device | Mar 10, 2009 | Issued |
Array
(
[id] => 9470738
[patent_doc_number] => 08724381
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-05-13
[patent_title] => 'Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding'
[patent_app_type] => utility
[patent_app_number] => 12/920407
[patent_app_country] => US
[patent_app_date] => 2009-03-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 8167
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12920407
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/920407 | Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding | Mar 10, 2009 | Issued |
Array
(
[id] => 5532134
[patent_doc_number] => 20090231922
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-09-17
[patent_title] => 'Nonvolatile Memory Device and Read Method Thereof'
[patent_app_type] => utility
[patent_app_number] => 12/396937
[patent_app_country] => US
[patent_app_date] => 2009-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4389
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0231/20090231922.pdf
[firstpage_image] =>[orig_patent_app_number] => 12396937
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/396937 | Nonvolatile memory device and read method thereof | Mar 2, 2009 | Issued |
Array
(
[id] => 4625621
[patent_doc_number] => 08004927
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-23
[patent_title] => 'Reversible-polarity decoder circuit and method'
[patent_app_type] => utility
[patent_app_number] => 12/396461
[patent_app_country] => US
[patent_app_date] => 2009-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 24
[patent_no_of_words] => 21672
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/004/08004927.pdf
[firstpage_image] =>[orig_patent_app_number] => 12396461
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/396461 | Reversible-polarity decoder circuit and method | Mar 1, 2009 | Issued |
Array
(
[id] => 5513328
[patent_doc_number] => 20090213634
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-08-27
[patent_title] => 'STACKED MEMORY AND FUSE CHIP'
[patent_app_type] => utility
[patent_app_number] => 12/392547
[patent_app_country] => US
[patent_app_date] => 2009-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 7437
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0213/20090213634.pdf
[firstpage_image] =>[orig_patent_app_number] => 12392547
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/392547 | Stacked memory and fuse chip | Feb 24, 2009 | Issued |
Array
(
[id] => 4464962
[patent_doc_number] => 07881089
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-01
[patent_title] => 'Coding techniques for improving the sense margin in content addressable memories'
[patent_app_type] => utility
[patent_app_number] => 12/392049
[patent_app_country] => US
[patent_app_date] => 2009-02-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6935
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/881/07881089.pdf
[firstpage_image] =>[orig_patent_app_number] => 12392049
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/392049 | Coding techniques for improving the sense margin in content addressable memories | Feb 23, 2009 | Issued |
Array
(
[id] => 8803551
[patent_doc_number] => 08441830
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-05-14
[patent_title] => 'Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device'
[patent_app_type] => utility
[patent_app_number] => 12/919799
[patent_app_country] => US
[patent_app_date] => 2009-02-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 9233
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 64
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12919799
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/919799 | Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device | Feb 22, 2009 | Issued |
Array
(
[id] => 5544351
[patent_doc_number] => 20090154228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-06-18
[patent_title] => 'Random Access Memory Employing Read Before Write for Resistance Stabilization'
[patent_app_type] => utility
[patent_app_number] => 12/371856
[patent_app_country] => US
[patent_app_date] => 2009-02-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 4099
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0154/20090154228.pdf
[firstpage_image] =>[orig_patent_app_number] => 12371856
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/371856 | Random access memory employing read before write for resistance stabilization | Feb 15, 2009 | Issued |
Array
(
[id] => 4601667
[patent_doc_number] => 07978505
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-07-12
[patent_title] => 'Heat assisted switching and separated read-write MRAM'
[patent_app_type] => utility
[patent_app_number] => 12/322107
[patent_app_country] => US
[patent_app_date] => 2009-01-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 9
[patent_no_of_words] => 9782
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 373
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/978/07978505.pdf
[firstpage_image] =>[orig_patent_app_number] => 12322107
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/322107 | Heat assisted switching and separated read-write MRAM | Jan 28, 2009 | Issued |
Array
(
[id] => 6444938
[patent_doc_number] => 20100188905
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-29
[patent_title] => 'Spin Device'
[patent_app_type] => utility
[patent_app_number] => 12/358721
[patent_app_country] => US
[patent_app_date] => 2009-01-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 17854
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0188/20100188905.pdf
[firstpage_image] =>[orig_patent_app_number] => 12358721
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/358721 | Spin device | Jan 22, 2009 | Issued |
Array
(
[id] => 94685
[patent_doc_number] => 07733722
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-06-08
[patent_title] => 'Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse'
[patent_app_type] => utility
[patent_app_number] => 12/351908
[patent_app_country] => US
[patent_app_date] => 2009-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2054
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/733/07733722.pdf
[firstpage_image] =>[orig_patent_app_number] => 12351908
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/351908 | Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse | Jan 11, 2009 | Issued |
Array
(
[id] => 4615352
[patent_doc_number] => 07990799
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-08-02
[patent_title] => 'Semiconductor memory device that includes an address coding method for a multi-word line test'
[patent_app_type] => utility
[patent_app_number] => 12/318685
[patent_app_country] => US
[patent_app_date] => 2009-01-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 6613
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/990/07990799.pdf
[firstpage_image] =>[orig_patent_app_number] => 12318685
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/318685 | Semiconductor memory device that includes an address coding method for a multi-word line test | Jan 5, 2009 | Issued |