Search

Nam Thanh Nguyen

Examiner (ID: 15670)

Most Active Art Unit
2824
Art Unit(s)
CSDE, 2824
Total Applications
700
Issued Applications
674
Pending Applications
6
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4491842 [patent_doc_number] => 07903475 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-08 [patent_title] => 'Latch pulse delay control' [patent_app_type] => utility [patent_app_number] => 12/416433 [patent_app_country] => US [patent_app_date] => 2009-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5617 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/903/07903475.pdf [firstpage_image] =>[orig_patent_app_number] => 12416433 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/416433
Latch pulse delay control Mar 31, 2009 Issued
Array ( [id] => 5354098 [patent_doc_number] => 20090185442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-07-23 [patent_title] => 'MEMORY SYSTEM AND METHOD WITH SERIAL AND PARALLEL MODES' [patent_app_type] => utility [patent_app_number] => 12/412968 [patent_app_country] => US [patent_app_date] => 2009-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7031 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20090185442.pdf [firstpage_image] =>[orig_patent_app_number] => 12412968 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/412968
Memory system and method with serial and parallel modes Mar 26, 2009 Issued
Array ( [id] => 35044 [patent_doc_number] => 07791961 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Semiconductor device and method for boosting word line' [patent_app_type] => utility [patent_app_number] => 12/406845 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 10553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/791/07791961.pdf [firstpage_image] =>[orig_patent_app_number] => 12406845 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/406845
Semiconductor device and method for boosting word line Mar 17, 2009 Issued
Array ( [id] => 5396408 [patent_doc_number] => 20090316471 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-12-24 [patent_title] => 'RESISTANCE CHANGE MEMORY' [patent_app_type] => utility [patent_app_number] => 12/404115 [patent_app_country] => US [patent_app_date] => 2009-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6679 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0316/20090316471.pdf [firstpage_image] =>[orig_patent_app_number] => 12404115 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/404115
Resistance change memory Mar 12, 2009 Issued
Array ( [id] => 5384365 [patent_doc_number] => 20090225609 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/402151 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 20152 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20090225609.pdf [firstpage_image] =>[orig_patent_app_number] => 12402151 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/402151
Semiconductor memory device Mar 10, 2009 Issued
Array ( [id] => 9470738 [patent_doc_number] => 08724381 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-13 [patent_title] => 'Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding' [patent_app_type] => utility [patent_app_number] => 12/920407 [patent_app_country] => US [patent_app_date] => 2009-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8167 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12920407 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/920407
Methods and apparatus for storing data in a multi-level cell flash memory device with cross-page sectors, multi-page coding and per-page coding Mar 10, 2009 Issued
Array ( [id] => 5532134 [patent_doc_number] => 20090231922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'Nonvolatile Memory Device and Read Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/396937 [patent_app_country] => US [patent_app_date] => 2009-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231922.pdf [firstpage_image] =>[orig_patent_app_number] => 12396937 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/396937
Nonvolatile memory device and read method thereof Mar 2, 2009 Issued
Array ( [id] => 4625621 [patent_doc_number] => 08004927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-23 [patent_title] => 'Reversible-polarity decoder circuit and method' [patent_app_type] => utility [patent_app_number] => 12/396461 [patent_app_country] => US [patent_app_date] => 2009-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 21672 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/004/08004927.pdf [firstpage_image] =>[orig_patent_app_number] => 12396461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/396461
Reversible-polarity decoder circuit and method Mar 1, 2009 Issued
Array ( [id] => 5513328 [patent_doc_number] => 20090213634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-27 [patent_title] => 'STACKED MEMORY AND FUSE CHIP' [patent_app_type] => utility [patent_app_number] => 12/392547 [patent_app_country] => US [patent_app_date] => 2009-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7437 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20090213634.pdf [firstpage_image] =>[orig_patent_app_number] => 12392547 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/392547
Stacked memory and fuse chip Feb 24, 2009 Issued
Array ( [id] => 4464962 [patent_doc_number] => 07881089 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-01 [patent_title] => 'Coding techniques for improving the sense margin in content addressable memories' [patent_app_type] => utility [patent_app_number] => 12/392049 [patent_app_country] => US [patent_app_date] => 2009-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6935 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/881/07881089.pdf [firstpage_image] =>[orig_patent_app_number] => 12392049 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/392049
Coding techniques for improving the sense margin in content addressable memories Feb 23, 2009 Issued
Array ( [id] => 8803551 [patent_doc_number] => 08441830 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device' [patent_app_type] => utility [patent_app_number] => 12/919799 [patent_app_country] => US [patent_app_date] => 2009-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 9233 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12919799 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/919799
Manufacturing method for stacking memory circuits and for addressing a memory circuit, corresponding stacking and device Feb 22, 2009 Issued
Array ( [id] => 5544351 [patent_doc_number] => 20090154228 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-18 [patent_title] => 'Random Access Memory Employing Read Before Write for Resistance Stabilization' [patent_app_type] => utility [patent_app_number] => 12/371856 [patent_app_country] => US [patent_app_date] => 2009-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4099 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20090154228.pdf [firstpage_image] =>[orig_patent_app_number] => 12371856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371856
Random access memory employing read before write for resistance stabilization Feb 15, 2009 Issued
Array ( [id] => 4601667 [patent_doc_number] => 07978505 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Heat assisted switching and separated read-write MRAM' [patent_app_type] => utility [patent_app_number] => 12/322107 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9782 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978505.pdf [firstpage_image] =>[orig_patent_app_number] => 12322107 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/322107
Heat assisted switching and separated read-write MRAM Jan 28, 2009 Issued
Array ( [id] => 6444938 [patent_doc_number] => 20100188905 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-29 [patent_title] => 'Spin Device' [patent_app_type] => utility [patent_app_number] => 12/358721 [patent_app_country] => US [patent_app_date] => 2009-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 17854 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0188/20100188905.pdf [firstpage_image] =>[orig_patent_app_number] => 12358721 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/358721
Spin device Jan 22, 2009 Issued
Array ( [id] => 94685 [patent_doc_number] => 07733722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-08 [patent_title] => 'Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse' [patent_app_type] => utility [patent_app_number] => 12/351908 [patent_app_country] => US [patent_app_date] => 2009-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2054 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/733/07733722.pdf [firstpage_image] =>[orig_patent_app_number] => 12351908 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/351908
Apparatus for implementing eFuse sense amplifier testing without blowing the eFuse Jan 11, 2009 Issued
Array ( [id] => 4615352 [patent_doc_number] => 07990799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-02 [patent_title] => 'Semiconductor memory device that includes an address coding method for a multi-word line test' [patent_app_type] => utility [patent_app_number] => 12/318685 [patent_app_country] => US [patent_app_date] => 2009-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 6613 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990799.pdf [firstpage_image] =>[orig_patent_app_number] => 12318685 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/318685
Semiconductor memory device that includes an address coding method for a multi-word line test Jan 5, 2009 Issued
Array ( [id] => 4492406 [patent_doc_number] => 07885115 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Non-volatile memory devices and methods of operating non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/318651 [patent_app_country] => US [patent_app_date] => 2009-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 6675 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/885/07885115.pdf [firstpage_image] =>[orig_patent_app_number] => 12318651 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/318651
Non-volatile memory devices and methods of operating non-volatile memory devices Jan 4, 2009 Issued
Array ( [id] => 6276713 [patent_doc_number] => 20100118618 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-13 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT WITH DATA BUS INVERSION FUNCTION' [patent_app_type] => utility [patent_app_number] => 12/345763 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2692 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20100118618.pdf [firstpage_image] =>[orig_patent_app_number] => 12345763 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345763
Semiconductor integrated circuit with data bus inversion function Dec 29, 2008 Issued
Array ( [id] => 4601712 [patent_doc_number] => 07978551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Bit line equalizing control circuit of a semiconductor memory apparatus' [patent_app_type] => utility [patent_app_number] => 12/345777 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4508 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978551.pdf [firstpage_image] =>[orig_patent_app_number] => 12345777 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345777
Bit line equalizing control circuit of a semiconductor memory apparatus Dec 29, 2008 Issued
Array ( [id] => 6403912 [patent_doc_number] => 20100165772 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'Self aligned back-gate for floating body cell memory erase' [patent_app_type] => utility [patent_app_number] => 12/319103 [patent_app_country] => US [patent_app_date] => 2008-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2592 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165772.pdf [firstpage_image] =>[orig_patent_app_number] => 12319103 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/319103
Self aligned back-gate for floating body cell memory erase Dec 29, 2008 Abandoned
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