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Nam Thanh Nguyen

Examiner (ID: 15670)

Most Active Art Unit
2824
Art Unit(s)
CSDE, 2824
Total Applications
700
Issued Applications
674
Pending Applications
6
Abandoned Applications
24

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6403746 [patent_doc_number] => 20100165748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'ERASE COMPLETION RECOGNITION' [patent_app_type] => utility [patent_app_number] => 12/345511 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3001 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20100165748.pdf [firstpage_image] =>[orig_patent_app_number] => 12345511 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345511
Erase completion recognition Dec 28, 2008 Issued
Array ( [id] => 5457133 [patent_doc_number] => 20090257285 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-15 [patent_title] => 'SEMICONDUCTOR MEMORY APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/345205 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4679 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20090257285.pdf [firstpage_image] =>[orig_patent_app_number] => 12345205 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345205
Semiconductor memory apparatus Dec 28, 2008 Issued
Array ( [id] => 4522351 [patent_doc_number] => 07911875 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Address counting circuit and semiconductor memory apparatus using the same' [patent_app_type] => utility [patent_app_number] => 12/345199 [patent_app_country] => US [patent_app_date] => 2008-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2805 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911875.pdf [firstpage_image] =>[orig_patent_app_number] => 12345199 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/345199
Address counting circuit and semiconductor memory apparatus using the same Dec 28, 2008 Issued
Array ( [id] => 4601690 [patent_doc_number] => 07978529 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-12 [patent_title] => 'Rewritable single-bit-per-cell flash memory' [patent_app_type] => utility [patent_app_number] => 12/344157 [patent_app_country] => US [patent_app_date] => 2008-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3648 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978529.pdf [firstpage_image] =>[orig_patent_app_number] => 12344157 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/344157
Rewritable single-bit-per-cell flash memory Dec 23, 2008 Issued
Array ( [id] => 4480811 [patent_doc_number] => 07869258 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-11 [patent_title] => 'Reverse set with current limit for non-volatile storage' [patent_app_type] => utility [patent_app_number] => 12/339313 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 13796 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/869/07869258.pdf [firstpage_image] =>[orig_patent_app_number] => 12339313 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339313
Reverse set with current limit for non-volatile storage Dec 18, 2008 Issued
Array ( [id] => 4601669 [patent_doc_number] => 07978507 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-12 [patent_title] => 'Pulse reset for non-volatile storage' [patent_app_type] => utility [patent_app_number] => 12/339363 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 29 [patent_no_of_words] => 13887 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/978/07978507.pdf [firstpage_image] =>[orig_patent_app_number] => 12339363 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339363
Pulse reset for non-volatile storage Dec 18, 2008 Issued
Array ( [id] => 5568575 [patent_doc_number] => 20090251953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-10-08 [patent_title] => 'Variable resistance memory device' [patent_app_type] => utility [patent_app_number] => 12/314965 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20090251953.pdf [firstpage_image] =>[orig_patent_app_number] => 12314965 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/314965
Variable resistance memory device Dec 18, 2008 Issued
Array ( [id] => 55585 [patent_doc_number] => 07773430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'Method of identifying logical information in a programming and erasing cell by on-side reading scheme' [patent_app_type] => utility [patent_app_number] => 12/314881 [patent_app_country] => US [patent_app_date] => 2008-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 3590 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/773/07773430.pdf [firstpage_image] =>[orig_patent_app_number] => 12314881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/314881
Method of identifying logical information in a programming and erasing cell by on-side reading scheme Dec 17, 2008 Issued
Array ( [id] => 4507035 [patent_doc_number] => 07920436 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Sense amplifier' [patent_app_type] => utility [patent_app_number] => 12/336965 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3122 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920436.pdf [firstpage_image] =>[orig_patent_app_number] => 12336965 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/336965
Sense amplifier Dec 16, 2008 Issued
Array ( [id] => 6403990 [patent_doc_number] => 20100148839 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-17 [patent_title] => 'Self-Tuning Of Signal Path Delay In Circuit Employing Multiple Voltage Domains' [patent_app_type] => utility [patent_app_number] => 12/336741 [patent_app_country] => US [patent_app_date] => 2008-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7482 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20100148839.pdf [firstpage_image] =>[orig_patent_app_number] => 12336741 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/336741
Self-tuning of signal path delay in circuit employing multiple voltage domains Dec 16, 2008 Issued
Array ( [id] => 4503965 [patent_doc_number] => 07948821 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-24 [patent_title] => 'Reduced signal interface memory device, system, and method' [patent_app_type] => utility [patent_app_number] => 12/334523 [patent_app_country] => US [patent_app_date] => 2008-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3766 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/948/07948821.pdf [firstpage_image] =>[orig_patent_app_number] => 12334523 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/334523
Reduced signal interface memory device, system, and method Dec 14, 2008 Issued
Array ( [id] => 229849 [patent_doc_number] => 07602666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-13 [patent_title] => 'Method of forming a unique number' [patent_app_type] => utility [patent_app_number] => 12/335163 [patent_app_country] => US [patent_app_date] => 2008-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 5696 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602666.pdf [firstpage_image] =>[orig_patent_app_number] => 12335163 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/335163
Method of forming a unique number Dec 14, 2008 Issued
Array ( [id] => 5532111 [patent_doc_number] => 20090231899 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-17 [patent_title] => 'PHASE CHANGE RANDOM ACCESS MEMORY AND LAYOUT METHOD OF THE SAME' [patent_app_type] => utility [patent_app_number] => 12/332787 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10060 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20090231899.pdf [firstpage_image] =>[orig_patent_app_number] => 12332787 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/332787
Phase change random access memory and layout method of the same Dec 10, 2008 Issued
Array ( [id] => 5390370 [patent_doc_number] => 20090207683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-20 [patent_title] => 'INPUT CIRCUIT OF SEMICONDUCTOR MEMORY APPARATUS AND CONTROLLING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 12/333143 [patent_app_country] => US [patent_app_date] => 2008-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5670 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20090207683.pdf [firstpage_image] =>[orig_patent_app_number] => 12333143 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/333143
Input circuit of semiconductor memory apparatus and controlling method thereof Dec 10, 2008 Issued
Array ( [id] => 4467820 [patent_doc_number] => 07936590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Digitally-controllable delay for sense amplifier' [patent_app_type] => utility [patent_app_number] => 12/329941 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7318 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/936/07936590.pdf [firstpage_image] =>[orig_patent_app_number] => 12329941 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329941
Digitally-controllable delay for sense amplifier Dec 7, 2008 Issued
Array ( [id] => 8117285 [patent_doc_number] => 08159864 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-04-17 [patent_title] => 'Data integrity preservation in spin transfer torque magnetoresistive random access memory' [patent_app_type] => utility [patent_app_number] => 12/329849 [patent_app_country] => US [patent_app_date] => 2008-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3963 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/159/08159864.pdf [firstpage_image] =>[orig_patent_app_number] => 12329849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329849
Data integrity preservation in spin transfer torque magnetoresistive random access memory Dec 7, 2008 Issued
Array ( [id] => 4581714 [patent_doc_number] => 07859901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 12/329007 [patent_app_country] => US [patent_app_date] => 2008-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 9107 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859901.pdf [firstpage_image] =>[orig_patent_app_number] => 12329007 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/329007
Semiconductor memory device Dec 4, 2008 Issued
Array ( [id] => 4507021 [patent_doc_number] => 07920432 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-05 [patent_title] => 'Semiconductor device having resistance based memory array, method of reading, and systems associated therewith' [patent_app_type] => utility [patent_app_number] => 12/292897 [patent_app_country] => US [patent_app_date] => 2008-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 26 [patent_no_of_words] => 8274 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/920/07920432.pdf [firstpage_image] =>[orig_patent_app_number] => 12292897 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/292897
Semiconductor device having resistance based memory array, method of reading, and systems associated therewith Nov 27, 2008 Issued
Array ( [id] => 4584591 [patent_doc_number] => 07826273 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-02 [patent_title] => 'Method of verifying programming of a nonvolatile memory device' [patent_app_type] => utility [patent_app_number] => 12/324713 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5655 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/826/07826273.pdf [firstpage_image] =>[orig_patent_app_number] => 12324713 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/324713
Method of verifying programming of a nonvolatile memory device Nov 25, 2008 Issued
Array ( [id] => 6564903 [patent_doc_number] => 20100128551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-05-27 [patent_title] => 'ADJUSTABLE VOLTAGE REGULATOR FOR PROVIDING A REGULATED OUTPUT VOLTAGE' [patent_app_type] => utility [patent_app_number] => 12/324375 [patent_app_country] => US [patent_app_date] => 2008-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4834 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20100128551.pdf [firstpage_image] =>[orig_patent_app_number] => 12324375 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/324375
Adjustable voltage regulator for providing a regulated output voltage Nov 25, 2008 Issued
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