Search

Nancy V Le

Director (ID: 1982, Phone: (571)272-4056 , Office: P/2400 )

Most Active Art Unit
2108
Art Unit(s)
2108, 2853, 2858, 2107, 2861
Total Applications
431
Issued Applications
255
Pending Applications
24
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 12989938 [patent_doc_number] => 20170345713 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-30 [patent_title] => SEMICONDUCTOR CHIPS HAVING THROUGH SILICON VIAS AND RELATED FABRICATION METHODS AND SEMICONDUCTOR PACKAGES [patent_app_type] => utility [patent_app_number] => 15/638551 [patent_app_country] => US [patent_app_date] => 2017-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11186 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15638551 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/638551
SEMICONDUCTOR CHIPS HAVING THROUGH SILICON VIAS AND RELATED FABRICATION METHODS AND SEMICONDUCTOR PACKAGES Jun 29, 2017 Abandoned
Array ( [id] => 11983735 [patent_doc_number] => 20170287890 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-10-05 [patent_title] => 'SEMICONDUCTOR PACKAGE STRUCTURE' [patent_app_type] => utility [patent_app_number] => 15/628745 [patent_app_country] => US [patent_app_date] => 2017-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4834 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15628745 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/628745
Bonding structure between semiconductor device package Jun 20, 2017 Issued
Array ( [id] => 13187911 [patent_doc_number] => 10109482 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Method for treating surface of semiconductor layer, semiconductor substrate, method for making epitaxial substrate [patent_app_type] => utility [patent_app_number] => 15/616562 [patent_app_country] => US [patent_app_date] => 2017-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 19 [patent_no_of_words] => 6771 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15616562 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/616562
Method for treating surface of semiconductor layer, semiconductor substrate, method for making epitaxial substrate Jun 6, 2017 Issued
Array ( [id] => 16264726 [patent_doc_number] => 10756174 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-25 [patent_title] => Multiple-stacked semiconductor nanowires and source/drain spacers [patent_app_type] => utility [patent_app_number] => 15/613339 [patent_app_country] => US [patent_app_date] => 2017-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 73 [patent_figures_cnt] => 73 [patent_no_of_words] => 8222 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15613339 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/613339
Multiple-stacked semiconductor nanowires and source/drain spacers Jun 4, 2017 Issued
Array ( [id] => 12181915 [patent_doc_number] => 20180040851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-02-08 [patent_title] => 'DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/611334 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611334 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611334
DISPLAY DEVICE AND METHOD FOR MANUFACTURING THE SAME May 31, 2017 Abandoned
Array ( [id] => 12554115 [patent_doc_number] => 10014263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Package assembly for embedded die and associated techniques and configurations [patent_app_type] => utility [patent_app_number] => 15/611428 [patent_app_country] => US [patent_app_date] => 2017-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 8706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15611428 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/611428
Package assembly for embedded die and associated techniques and configurations May 31, 2017 Issued
Array ( [id] => 12093742 [patent_doc_number] => 20170350835 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-07 [patent_title] => 'INTEGRATION OF MONOLAYER GRAPHENE WITH A SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/609706 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3653 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609706 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609706
Integration of monolayer graphene with a semiconductor device May 30, 2017 Issued
Array ( [id] => 14268183 [patent_doc_number] => 10283664 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-05-07 [patent_title] => Avalanche diode including vertical PN junction [patent_app_type] => utility [patent_app_number] => 15/609854 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 24 [patent_no_of_words] => 5298 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609854 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609854
Avalanche diode including vertical PN junction May 30, 2017 Issued
Array ( [id] => 13598785 [patent_doc_number] => 20180350941 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => THROUGH-SUBSTRATE VIA POWER GATING AND DELIVERY BIPOLAR TRANSISTOR [patent_app_type] => utility [patent_app_number] => 15/609814 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5114 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609814 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609814
Through-substrate via power gating and delivery bipolar transistor May 30, 2017 Issued
Array ( [id] => 12850222 [patent_doc_number] => 20180175247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => SEMICONDUCTOR LIGHT-EMITTING DEVICE [patent_app_type] => utility [patent_app_number] => 15/609653 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7160 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609653 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609653
SEMICONDUCTOR LIGHT-EMITTING DEVICE May 30, 2017 Abandoned
Array ( [id] => 13293283 [patent_doc_number] => 10157842 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-12-18 [patent_title] => Semiconductor device including superconducting metal through-silicon-vias and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/609860 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 5312 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609860 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609860
Semiconductor device including superconducting metal through-silicon-vias and method of manufacturing the same May 30, 2017 Issued
Array ( [id] => 15061495 [patent_doc_number] => 10461060 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Structure and formation method of chip package with redistribution layers [patent_app_type] => utility [patent_app_number] => 15/609743 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6591 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609743 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609743
Structure and formation method of chip package with redistribution layers May 30, 2017 Issued
Array ( [id] => 13599059 [patent_doc_number] => 20180351078 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SHIELDED SEMICONDUCTOR DEVICES AND METHODS FOR FABRICATING SHIELDED SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 15/609621 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609621 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609621
Shielded magnetoresistive random access memory devices and methods for fabricating the same May 30, 2017 Issued
Array ( [id] => 15065081 [patent_doc_number] => 10462876 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-29 [patent_title] => Light emitting diode sensor device including a contoured structure [patent_app_type] => utility [patent_app_number] => 15/609879 [patent_app_country] => US [patent_app_date] => 2017-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 9115 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15609879 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/609879
Light emitting diode sensor device including a contoured structure May 30, 2017 Issued
Array ( [id] => 14889243 [patent_doc_number] => 10424673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Semiconductor device including a stack of oxide semiconductor layers [patent_app_type] => utility [patent_app_number] => 15/605132 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 46 [patent_no_of_words] => 24332 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605132 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605132
Semiconductor device including a stack of oxide semiconductor layers May 24, 2017 Issued
Array ( [id] => 11959634 [patent_doc_number] => 20170263786 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'OXIDE SEMICONDUCTOR SUBSTRATE AND SCHOTTKY BARRIER DIODE' [patent_app_type] => utility [patent_app_number] => 15/605779 [patent_app_country] => US [patent_app_date] => 2017-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 10317 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15605779 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/605779
Oxide semiconductor substrate and schottky barrier diode May 24, 2017 Issued
Array ( [id] => 13559553 [patent_doc_number] => 20180331324 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => LIGHT OUT-COUPLING IN ORGANIC LIGHT-EMITTING DIODES (OLED) [patent_app_type] => utility [patent_app_number] => 15/591236 [patent_app_country] => US [patent_app_date] => 2017-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2351 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15591236 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/591236
LIGHT OUT-COUPLING IN ORGANIC LIGHT-EMITTING DIODES (OLED) May 9, 2017 Abandoned
Array ( [id] => 13695213 [patent_doc_number] => 20170358561 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-12-14 [patent_title] => LED LEADFRAME AND LED PACKAGING STRUCTURE [patent_app_type] => utility [patent_app_number] => 15/588721 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588721 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588721
LED LEADFRAME AND LED PACKAGING STRUCTURE May 7, 2017 Abandoned
Array ( [id] => 15015375 [patent_doc_number] => 10453848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-10-22 [patent_title] => Dynamic random access memory structure along with guard ring structure and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 15/588713 [patent_app_country] => US [patent_app_date] => 2017-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4873 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15588713 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/588713
Dynamic random access memory structure along with guard ring structure and manufacturing method thereof May 7, 2017 Issued
Array ( [id] => 14738577 [patent_doc_number] => 10388699 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-08-20 [patent_title] => Three-dimensional semiconductor memory devices [patent_app_type] => utility [patent_app_number] => 15/586307 [patent_app_country] => US [patent_app_date] => 2017-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 10967 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15586307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/586307
Three-dimensional semiconductor memory devices May 3, 2017 Issued
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