Search

Nancy V Le

Director (ID: 1982, Phone: (571)272-4056 , Office: P/2400 )

Most Active Art Unit
2108
Art Unit(s)
2108, 2853, 2858, 2107, 2861
Total Applications
431
Issued Applications
255
Pending Applications
24
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11652859 [patent_doc_number] => 20170148760 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-05-25 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => utility [patent_app_number] => 15/316574 [patent_app_country] => US [patent_app_date] => 2015-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 41 [patent_no_of_words] => 25920 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15316574 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/316574
Semiconductor device and method of manufacturing the same Jun 4, 2015 Issued
Array ( [id] => 11063785 [patent_doc_number] => 20160260747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-09-08 [patent_title] => 'THIN FILM TRANSISTOR AND METHOD OF MANUFACTURING THE SAME, ARRAY SUBSTRATE AND DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/785408 [patent_app_country] => US [patent_app_date] => 2015-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5488 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14785408 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/785408
Thin film transistor and method of manufacturing the same, array substrate and display apparatus Apr 23, 2015 Issued
Array ( [id] => 11307678 [patent_doc_number] => 09515084 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-12-06 [patent_title] => '3D nonvolatile memory device having common word line' [patent_app_type] => utility [patent_app_number] => 14/667397 [patent_app_country] => US [patent_app_date] => 2015-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 3989 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14667397 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/667397
3D nonvolatile memory device having common word line Mar 23, 2015 Issued
Array ( [id] => 11300541 [patent_doc_number] => 09508551 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-11-29 [patent_title] => 'Method of fabricating a semiconductor device and a semiconductor device fabricated by the method' [patent_app_type] => utility [patent_app_number] => 14/665141 [patent_app_country] => US [patent_app_date] => 2015-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 39 [patent_figures_cnt] => 39 [patent_no_of_words] => 10284 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14665141 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/665141
Method of fabricating a semiconductor device and a semiconductor device fabricated by the method Mar 22, 2015 Issued
Array ( [id] => 10809594 [patent_doc_number] => 20160155753 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-02 [patent_title] => 'DISPLAY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/664589 [patent_app_country] => US [patent_app_date] => 2015-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7358 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14664589 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/664589
DISPLAY DEVICE Mar 19, 2015 Abandoned
Array ( [id] => 12109115 [patent_doc_number] => 09865603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-09 [patent_title] => 'Transistor structure having N-type and P-type elongated regions intersecting under common gate' [patent_app_type] => utility [patent_app_number] => 14/662734 [patent_app_country] => US [patent_app_date] => 2015-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 4356 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14662734 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/662734
Transistor structure having N-type and P-type elongated regions intersecting under common gate Mar 18, 2015 Issued
Array ( [id] => 10426302 [patent_doc_number] => 20150311313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-29 [patent_title] => 'SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/661944 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8805 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14661944 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/661944
Semiconductor device and manufacturing method thereof Mar 17, 2015 Issued
Array ( [id] => 11847545 [patent_doc_number] => 09735102 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'High voltage device' [patent_app_type] => utility [patent_app_number] => 14/660955 [patent_app_country] => US [patent_app_date] => 2015-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 43 [patent_no_of_words] => 7261 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660955 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660955
High voltage device Mar 17, 2015 Issued
Array ( [id] => 10409925 [patent_doc_number] => 20150294934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-15 [patent_title] => 'Semiconductor Device Including Fully-Silicided Liner Extending Over Respective A Contact Plug And An Insulating Layer' [patent_app_type] => utility [patent_app_number] => 14/660759 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 3792 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660759 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660759
Semiconductor device including fully-silicided liner extending over a contact plug and insulating layer Mar 16, 2015 Issued
Array ( [id] => 10418177 [patent_doc_number] => 20150303187 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'BiCMOS Integration Using a Shared SiGe Layer' [patent_app_type] => utility [patent_app_number] => 14/659974 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5528 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14659974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/659974
BiCMOS integration using a shared SiGe layer Mar 16, 2015 Issued
Array ( [id] => 12047180 [patent_doc_number] => 09824788 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-21 [patent_title] => 'Metal wire having a copper layer and a barrier layer and display device including the same' [patent_app_type] => utility [patent_app_number] => 14/659730 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 9580 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14659730 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/659730
Metal wire having a copper layer and a barrier layer and display device including the same Mar 16, 2015 Issued
Array ( [id] => 10418179 [patent_doc_number] => 20150303188 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'BiCMOS Integration with Reduced Masking Steps' [patent_app_type] => utility [patent_app_number] => 14/660084 [patent_app_country] => US [patent_app_date] => 2015-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6424 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14660084 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/660084
BiCMOS integration with reduced masking steps Mar 16, 2015 Issued
Array ( [id] => 10463895 [patent_doc_number] => 20150348909 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-03 [patent_title] => 'SEMICONDUCTOR DEVICE, MANUFACTURING METHOD THEREOF, AND ELECTRONIC DEVICE' [patent_app_type] => utility [patent_app_number] => 14/657347 [patent_app_country] => US [patent_app_date] => 2015-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 51539 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14657347 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/657347
Semiconductor device including insulating film having opening portion and conductive film in the opening portion Mar 12, 2015 Issued
Array ( [id] => 10733026 [patent_doc_number] => 20160079176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/656542 [patent_app_country] => US [patent_app_date] => 2015-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3185 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14656542 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/656542
SEMICONDUCTOR DEVICE Mar 11, 2015 Abandoned
Array ( [id] => 10733067 [patent_doc_number] => 20160079216 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-17 [patent_title] => 'SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/645343 [patent_app_country] => US [patent_app_date] => 2015-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9376 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14645343 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/645343
SEMICONDUCTOR DEVICE, AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE Mar 10, 2015 Abandoned
Array ( [id] => 10286046 [patent_doc_number] => 20150171044 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-18 [patent_title] => 'BBUL TOP SIDE SUBSTRATE LAYER ENABLING DUAL SIDED SILICON INTERCONNECT AND STACKING FLEXIBILITY' [patent_app_type] => utility [patent_app_number] => 14/629350 [patent_app_country] => US [patent_app_date] => 2015-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4214 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14629350 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/629350
BBUL top side substrate layer enabling dual sided silicon interconnect and stacking flexibility Feb 22, 2015 Issued
Array ( [id] => 10238134 [patent_doc_number] => 20150123127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/595664 [patent_app_country] => US [patent_app_date] => 2015-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 25595 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14595664 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/595664
Semiconductor device including pellet-like particle or flat-plate-like particle Jan 12, 2015 Issued
Array ( [id] => 10238132 [patent_doc_number] => 20150123126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-05-07 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/594991 [patent_app_country] => US [patent_app_date] => 2015-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 21470 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14594991 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/594991
Semiconductor device Jan 11, 2015 Issued
Array ( [id] => 11725186 [patent_doc_number] => 09698051 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-07-04 [patent_title] => 'Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages' [patent_app_type] => utility [patent_app_number] => 14/590036 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 29 [patent_no_of_words] => 11550 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590036 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590036
Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages Jan 5, 2015 Issued
Array ( [id] => 15703979 [patent_doc_number] => 10608177 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-31 [patent_title] => Self-gated RRAM cell and method for manufacturing the same [patent_app_type] => utility [patent_app_number] => 15/525200 [patent_app_country] => US [patent_app_date] => 2014-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5458 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15525200 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/525200
Self-gated RRAM cell and method for manufacturing the same Dec 25, 2014 Issued
Menu