Search

Nancy V Le

Director (ID: 1982, Phone: (571)272-4056 , Office: P/2400 )

Most Active Art Unit
2108
Art Unit(s)
2108, 2853, 2858, 2107, 2861
Total Applications
431
Issued Applications
255
Pending Applications
24
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 14801481 [patent_doc_number] => 10403752 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-03 [patent_title] => Prevention of subchannel leakage current in a semiconductor device with a fin structure [patent_app_type] => utility [patent_app_number] => 15/525183 [patent_app_country] => US [patent_app_date] => 2014-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4225 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15525183 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/525183
Prevention of subchannel leakage current in a semiconductor device with a fin structure Dec 21, 2014 Issued
Array ( [id] => 10322030 [patent_doc_number] => 20150207034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-23 [patent_title] => 'SEMICONDUCTOR LIGHT EMITTING DEVICE' [patent_app_type] => utility [patent_app_number] => 14/577826 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6075 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577826 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577826
SEMICONDUCTOR LIGHT EMITTING DEVICE Dec 18, 2014 Abandoned
Array ( [id] => 13188359 [patent_doc_number] => 10109707 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-10-23 [patent_title] => Crystalline multilayer oxide thin films structure in semiconductor device [patent_app_type] => utility [patent_app_number] => 14/577917 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4278 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577917 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577917
Crystalline multilayer oxide thin films structure in semiconductor device Dec 18, 2014 Issued
Array ( [id] => 10984420 [patent_doc_number] => 20160181365 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-06-23 [patent_title] => 'SEMICONDUCTOR DEVICES HAVING CHANNEL REGIONS WITH NON-UNIFORM EDGE' [patent_app_type] => utility [patent_app_number] => 14/577451 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5761 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577451 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577451
Semiconductor devices having channel regions with non-uniform edge Dec 18, 2014 Issued
Array ( [id] => 10217425 [patent_doc_number] => 20150102418 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-04-16 [patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/576268 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7742 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14576268 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/576268
SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE DEVICE Dec 18, 2014 Abandoned
Array ( [id] => 10302686 [patent_doc_number] => 20150187686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-07-02 [patent_title] => 'SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 14/577338 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1851 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577338 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577338
SEMICONDUCTOR DEVICE Dec 18, 2014 Abandoned
Array ( [id] => 10294864 [patent_doc_number] => 20150179863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'AVALANCHE PHOTODIODE UTILIZING INTERFACIAL MISFIT ARRAY' [patent_app_type] => utility [patent_app_number] => 14/577927 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 10258 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577927 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577927
AVALANCHE PHOTODIODE UTILIZING INTERFACIAL MISFIT ARRAY Dec 18, 2014 Abandoned
Array ( [id] => 10294430 [patent_doc_number] => 20150179429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-06-25 [patent_title] => 'METHOD FOR TREATING SURFACE OF SEMICONDUCTOR LAYER, SEMICONDUCTOR SUBSTRATE, METHOD FOR MAKING EPITAXIAL SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 14/577847 [patent_app_country] => US [patent_app_date] => 2014-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6844 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14577847 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/577847
METHOD FOR TREATING SURFACE OF SEMICONDUCTOR LAYER, SEMICONDUCTOR SUBSTRATE, METHOD FOR MAKING EPITAXIAL SUBSTRATE Dec 18, 2014 Abandoned
Array ( [id] => 12033863 [patent_doc_number] => 20170323962 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-11-09 [patent_title] => 'CARRIER CONFINEMENT FOR HIGH MOBILITY CHANNEL DEVICES' [patent_app_type] => utility [patent_app_number] => 15/525164 [patent_app_country] => US [patent_app_date] => 2014-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4948 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15525164 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/525164
Carrier confinement for high mobility channel devices Dec 16, 2014 Issued
Array ( [id] => 9905567 [patent_doc_number] => 20150060767 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-03-05 [patent_title] => 'NANOWIRES AND NANOWIRE FIELDE-EFFECT TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 14/536953 [patent_app_country] => US [patent_app_date] => 2014-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5259 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14536953 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/536953
NANOWIRES AND NANOWIRE FIELDE-EFFECT TRANSISTORS Nov 9, 2014 Abandoned
Array ( [id] => 9855098 [patent_doc_number] => 20150035115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-02-05 [patent_title] => 'MODIFIED VIA BOTTOM FOR BEOL VIA EFUSE' [patent_app_type] => utility [patent_app_number] => 14/520390 [patent_app_country] => US [patent_app_date] => 2014-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6020 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14520390 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/520390
Modified via bottom for beol via efuse Oct 21, 2014 Issued
Array ( [id] => 11876495 [patent_doc_number] => 09748276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-29 [patent_title] => 'Thin film transistor and method of manufacturing the same, array substrate and display device' [patent_app_type] => utility [patent_app_number] => 14/769438 [patent_app_country] => US [patent_app_date] => 2014-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 7851 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14769438 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/769438
Thin film transistor and method of manufacturing the same, array substrate and display device Oct 20, 2014 Issued
Array ( [id] => 11453228 [patent_doc_number] => 09576880 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-02-21 [patent_title] => 'Dual damascene structure with liner' [patent_app_type] => utility [patent_app_number] => 14/517131 [patent_app_country] => US [patent_app_date] => 2014-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14517131 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/517131
Dual damascene structure with liner Oct 16, 2014 Issued
Array ( [id] => 11898260 [patent_doc_number] => 09768202 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-19 [patent_title] => 'TFT backplate structure comprising transistors having gate isolation layers of different thicknesses and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 14/426155 [patent_app_country] => US [patent_app_date] => 2014-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3767 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 528 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14426155 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/426155
TFT backplate structure comprising transistors having gate isolation layers of different thicknesses and manufacture method thereof Sep 18, 2014 Issued
Array ( [id] => 12040641 [patent_doc_number] => 09818877 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-11-14 [patent_title] => 'Embedded source/drain structure for tall finFET and method of formation' [patent_app_type] => utility [patent_app_number] => 14/490274 [patent_app_country] => US [patent_app_date] => 2014-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 22 [patent_no_of_words] => 3792 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14490274 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/490274
Embedded source/drain structure for tall finFET and method of formation Sep 17, 2014 Issued
Array ( [id] => 12554313 [patent_doc_number] => 10014329 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-03 [patent_title] => Array substrate with thin film transistor and method of manufacturing the same [patent_app_type] => utility [patent_app_number] => 14/436843 [patent_app_country] => US [patent_app_date] => 2014-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 21 [patent_no_of_words] => 5088 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14436843 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/436843
Array substrate with thin film transistor and method of manufacturing the same Sep 10, 2014 Issued
Array ( [id] => 11050915 [patent_doc_number] => 20160247874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-25 [patent_title] => 'ARRAY SUBSTRATE AND MANUFACTURING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/443798 [patent_app_country] => US [patent_app_date] => 2014-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5399 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14443798 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/443798
Array substrate comprising a power wire layer and manufacturing method thereof Sep 3, 2014 Issued
Array ( [id] => 11925915 [patent_doc_number] => 09793506 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-10-17 [patent_title] => 'Display panel with annular protrusion and annular groove, packaging method thereof and display device' [patent_app_type] => utility [patent_app_number] => 14/439465 [patent_app_country] => US [patent_app_date] => 2014-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2614 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14439465 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/439465
Display panel with annular protrusion and annular groove, packaging method thereof and display device Sep 1, 2014 Issued
Array ( [id] => 11847673 [patent_doc_number] => 09735232 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-08-15 [patent_title] => 'Method for manufacturing a semiconductor structure having a trench with high aspect ratio' [patent_app_type] => utility [patent_app_number] => 14/339974 [patent_app_country] => US [patent_app_date] => 2014-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8966 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14339974 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/339974
Method for manufacturing a semiconductor structure having a trench with high aspect ratio Jul 23, 2014 Issued
Array ( [id] => 11710766 [patent_doc_number] => 20170179265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-22 [patent_title] => 'POWER SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 15/300583 [patent_app_country] => US [patent_app_date] => 2014-07-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2916 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15300583 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/300583
Power semiconductor device including a semiconductor switching element Jul 3, 2014 Issued
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