Nanda Bondade

Array ( [id] => 1060090 [patent_doc_number] => 06853034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-08 [patent_title] => 'Semiconductor device exhibiting a high breakdown voltage and the method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 09/756686 [patent_app_country] => US [patent_app_date] => 2001-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 36 [patent_no_of_words] => 10799 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/853/06853034.pdf [firstpage_image] =>[orig_patent_app_number] => 09756686 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1395535 [patent_doc_number] => 06548851 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-15 [patent_title] => 'Semiconductor memory device with increased level of integration' [patent_app_type] => B2 [patent_app_number] => 09/755086 [patent_app_country] => US [patent_app_date] => 2001-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2422 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548851.pdf [firstpage_image] =>[orig_patent_app_number] => 09755086 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1522266 [patent_doc_number] => 06414361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-02 [patent_title] => 'Buried shallow trench isolation and method for forming the same' [patent_app_type] => B2 [patent_app_number] => 09/754145 [patent_app_country] => US [patent_app_date] => 2001-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2902 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/414/06414361.pdf [firstpage_image] =>[orig_patent_app_number] => 09754145 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6571568 [patent_doc_number] => 20020084497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-04 [patent_title] => 'Composite transistor having a slew-rate control' [patent_app_type] => new [patent_app_number] => 09/754156 [patent_app_country] => US [patent_app_date] => 2001-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2367 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0084/20020084497.pdf [firstpage_image] =>[orig_patent_app_number] => 09754156 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 677114 [patent_doc_number] => 07087975 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Area efficient stacking of antifuses in semiconductor device' [patent_app_type] => utility [patent_app_number] => 09/751474 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 16 [patent_no_of_words] => 13179 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/087/07087975.pdf [firstpage_image] =>[orig_patent_app_number] => 09751474 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1459816 [patent_doc_number] => 06426517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-07-30 [patent_title] => 'Active matrix display device having multiple gate electrode portions' [patent_app_type] => B2 [patent_app_number] => 09/736139 [patent_app_country] => US [patent_app_date] => 2000-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 4325 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/426/06426517.pdf [firstpage_image] =>[orig_patent_app_number] => 09736139 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 951595 [patent_doc_number] => 06960800 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-01 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 09/734176 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 4312 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/960/06960800.pdf [firstpage_image] =>[orig_patent_app_number] => 09734176 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6875527 [patent_doc_number] => 20010000620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-05-03 [patent_title] => 'Thin film transistor and method of fabricating the same' [patent_app_type] => new-utility [patent_app_number] => 09/730875 [patent_app_country] => US [patent_app_date] => 2000-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6395 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000620.pdf [firstpage_image] =>[orig_patent_app_number] => 09730875 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1422288 [patent_doc_number] => 06518623 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Semiconductor device having a buried-channel MOS structure' [patent_app_type] => B1 [patent_app_number] => 09/718486 [patent_app_country] => US [patent_app_date] => 2000-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 36 [patent_no_of_words] => 8595 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518623.pdf [firstpage_image] =>[orig_patent_app_number] => 09718486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1302478 [patent_doc_number] => 06624493 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Biasing, operation and parasitic current limitation in single device equivalent to CMOS, and other semiconductor systems' [patent_app_type] => B1 [patent_app_number] => 09/716046 [patent_app_country] => US [patent_app_date] => 2000-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 31 [patent_no_of_words] => 21495 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624493.pdf [firstpage_image] =>[orig_patent_app_number] => 09716046 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7634340 [patent_doc_number] => 06657280 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Redundant interconnect high current bipolar device' [patent_app_type] => B1 [patent_app_number] => 09/711726 [patent_app_country] => US [patent_app_date] => 2000-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3535 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/657/06657280.pdf [firstpage_image] =>[orig_patent_app_number] => 09711726 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1229935 [patent_doc_number] => 06696722 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-24 [patent_title] => 'Storage node of DRAM cell' [patent_app_type] => B1 [patent_app_number] => 09/708957 [patent_app_country] => US [patent_app_date] => 2000-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2266 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/696/06696722.pdf [firstpage_image] =>[orig_patent_app_number] => 09708957 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1383913 [patent_doc_number] => 06559475 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Test pattern for evaluating a process of silicide film formation' [patent_app_type] => B1 [patent_app_number] => 09/704760 [patent_app_country] => US [patent_app_date] => 2000-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3738 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559475.pdf [firstpage_image] =>[orig_patent_app_number] => 09704760 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1424221 [patent_doc_number] => 06507071 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Lateral high-voltage sidewall transistor' [patent_app_type] => B1 [patent_app_number] => 09/694435 [patent_app_country] => US [patent_app_date] => 2000-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2498 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/507/06507071.pdf [firstpage_image] =>[orig_patent_app_number] => 09694435 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1375483 [patent_doc_number] => 06558996 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Edge structure for relaxing electric field of semiconductor device having an embedded type diffusion structure' [patent_app_type] => B1 [patent_app_number] => 09/691016 [patent_app_country] => US [patent_app_date] => 2000-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4882 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 321 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/558/06558996.pdf [firstpage_image] =>[orig_patent_app_number] => 09691016 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1302274 [patent_doc_number] => 06624469 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Vertical MOS transistor having body region formed by inclined ion implantation' [patent_app_type] => B1 [patent_app_number] => 09/690226 [patent_app_country] => US [patent_app_date] => 2000-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5866 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624469.pdf [firstpage_image] =>[orig_patent_app_number] => 09690226 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1299941 [patent_doc_number] => 06627925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Transistor having a novel layout and an emitter having more than one feed point' [patent_app_type] => B1 [patent_app_number] => 09/687381 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 48 [patent_no_of_words] => 7909 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/627/06627925.pdf [firstpage_image] =>[orig_patent_app_number] => 09687381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1178472 [patent_doc_number] => 06747313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'Thin film transistor' [patent_app_type] => B1 [patent_app_number] => 09/689746 [patent_app_country] => US [patent_app_date] => 2000-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 1823 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/747/06747313.pdf [firstpage_image] =>[orig_patent_app_number] => 09689746 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1390505 [patent_doc_number] => 06552361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Thin film transistor device' [patent_app_type] => B1 [patent_app_number] => 09/680935 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 1984 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552361.pdf [firstpage_image] =>[orig_patent_app_number] => 09680935 [rel_patent_id] =>[rel_patent_doc_number] =>)