
Nanda Bondade
Examiner (ID: 16161)
| Most Active Art Unit | 2912 |
| Art Unit(s) | 2912, 2900, 2902 |
| Total Applications | 5029 |
| Issued Applications | 4983 |
| Pending Applications | 0 |
| Abandoned Applications | 46 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4318246
[patent_doc_number] => 06316835
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-11-13
[patent_title] => 'Method for forming zig-zag bordered openings in semiconductor structures and structures formed'
[patent_app_type] => 1
[patent_app_number] => 9/113625
[patent_app_country] => US
[patent_app_date] => 1998-07-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2995
[patent_no_of_claims] => 2
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[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/316/06316835.pdf
[firstpage_image] =>[orig_patent_app_number] => 113625
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/113625 | Method for forming zig-zag bordered openings in semiconductor structures and structures formed | Jul 9, 1998 | Issued |
Array
(
[id] => 1550951
[patent_doc_number] => 06346737
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-02-12
[patent_title] => 'Shallow trench isolation process particularly suited for high voltage circuits'
[patent_app_type] => B1
[patent_app_number] => 09/109755
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 3132
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[pdf_file] => patents/06/346/06346737.pdf
[firstpage_image] =>[orig_patent_app_number] => 09109755
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/109755 | Shallow trench isolation process particularly suited for high voltage circuits | Jul 1, 1998 | Issued |
Array
(
[id] => 1448053
[patent_doc_number] => 06369420
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-09
[patent_title] => 'Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby'
[patent_app_type] => B1
[patent_app_number] => 09/110115
[patent_app_country] => US
[patent_app_date] => 1998-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 25
[patent_no_of_words] => 2778
[patent_no_of_claims] => 13
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[patent_words_short_claim] => 224
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/369/06369420.pdf
[firstpage_image] =>[orig_patent_app_number] => 09110115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/110115 | Method of self-aligning a floating gate to a control gate and to an isolation in an electrically erasable and programmable memory cell, and a cell made thereby | Jul 1, 1998 | Issued |
| 09/000255 | MODULATION-DOPED FIELD-EFFECT TRANSISTOR WITH A COMPOSITION- MODULATED BARRIER STRUCTURE | Jun 18, 1998 | Abandoned |
Array
(
[id] => 4158769
[patent_doc_number] => 06124607
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-26
[patent_title] => 'Capacitive memory cell'
[patent_app_type] => 1
[patent_app_number] => 9/096006
[patent_app_country] => US
[patent_app_date] => 1998-06-11
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[pdf_file] => patents/06/124/06124607.pdf
[firstpage_image] =>[orig_patent_app_number] => 096006
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/096006 | Capacitive memory cell | Jun 10, 1998 | Issued |
Array
(
[id] => 1518716
[patent_doc_number] => 06501094
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-12-31
[patent_title] => 'Semiconductor device comprising a bottom gate type thin film transistor'
[patent_app_type] => B1
[patent_app_number] => 09/095026
[patent_app_country] => US
[patent_app_date] => 1998-06-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
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[pdf_file] => patents/06/501/06501094.pdf
[firstpage_image] =>[orig_patent_app_number] => 09095026
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/095026 | Semiconductor device comprising a bottom gate type thin film transistor | Jun 8, 1998 | Issued |
Array
(
[id] => 1116968
[patent_doc_number] => 06800928
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-05
[patent_title] => 'Porous integrated circuit dielectric with decreased surface porosity'
[patent_app_type] => B1
[patent_app_number] => 09/087234
[patent_app_country] => US
[patent_app_date] => 1998-05-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
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[patent_no_of_words] => 5238
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[pdf_file] => patents/06/800/06800928.pdf
[firstpage_image] =>[orig_patent_app_number] => 09087234
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/087234 | Porous integrated circuit dielectric with decreased surface porosity | May 27, 1998 | Issued |
Array
(
[id] => 4183765
[patent_doc_number] => 06037615
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Metal semiconductor FET having doped A1GaAs layer between channel layer and A1GaAs buffer layer'
[patent_app_type] => 1
[patent_app_number] => 9/083934
[patent_app_country] => US
[patent_app_date] => 1998-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 2816
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[pdf_file] => patents/06/037/06037615.pdf
[firstpage_image] =>[orig_patent_app_number] => 083934
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/083934 | Metal semiconductor FET having doped A1GaAs layer between channel layer and A1GaAs buffer layer | May 25, 1998 | Issued |
Array
(
[id] => 4186889
[patent_doc_number] => 06020603
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Semiconductor device with a beveled and chamfered outer peripheral portion'
[patent_app_type] => 1
[patent_app_number] => 9/068974
[patent_app_country] => US
[patent_app_date] => 1998-05-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 3848
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[pdf_file] => patents/06/020/06020603.pdf
[firstpage_image] =>[orig_patent_app_number] => 068974
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/068974 | Semiconductor device with a beveled and chamfered outer peripheral portion | May 21, 1998 | Issued |
Array
(
[id] => 4091114
[patent_doc_number] => 06025652
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Semiconductor device and method of producing same'
[patent_app_type] => 1
[patent_app_number] => 9/081680
[patent_app_country] => US
[patent_app_date] => 1998-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[pdf_file] => patents/06/025/06025652.pdf
[firstpage_image] =>[orig_patent_app_number] => 081680
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/081680 | Semiconductor device and method of producing same | May 19, 1998 | Issued |
Array
(
[id] => 1544294
[patent_doc_number] => 06373113
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2002-04-16
[patent_title] => 'Nitrogenated gate structure for improved transistor performance and method for making same'
[patent_app_type] => B1
[patent_app_number] => 09/073755
[patent_app_country] => US
[patent_app_date] => 1998-05-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/06/373/06373113.pdf
[firstpage_image] =>[orig_patent_app_number] => 09073755
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/073755 | Nitrogenated gate structure for improved transistor performance and method for making same | May 5, 1998 | Issued |
Array
(
[id] => 4194990
[patent_doc_number] => 06153915
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-11-28
[patent_title] => 'CMOS semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 9/070915
[patent_app_country] => US
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[pdf_file] => patents/06/153/06153915.pdf
[firstpage_image] =>[orig_patent_app_number] => 070915
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070915 | CMOS semiconductor device | May 3, 1998 | Issued |
Array
(
[id] => 4366377
[patent_doc_number] => 06255710
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => '3-D smart power IC'
[patent_app_type] => 1
[patent_app_number] => 9/072339
[patent_app_country] => US
[patent_app_date] => 1998-05-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/255/06255710.pdf
[firstpage_image] =>[orig_patent_app_number] => 072339
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/072339 | 3-D smart power IC | May 3, 1998 | Issued |
Array
(
[id] => 4363466
[patent_doc_number] => 06169304
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-02
[patent_title] => 'Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer'
[patent_app_type] => 1
[patent_app_number] => 9/071534
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[patent_app_date] => 1998-05-04
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[pdf_file] => patents/06/169/06169304.pdf
[firstpage_image] =>[orig_patent_app_number] => 071534
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071534 | Semiconductor device having a passivation layer which minimizes diffusion of hydrogen into a dielectric layer | May 3, 1998 | Issued |
Array
(
[id] => 4340922
[patent_doc_number] => 06333528
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-12-25
[patent_title] => 'Semiconductor device having a capacitor exhibiting improved moisture resistance'
[patent_app_type] => 1
[patent_app_number] => 9/071795
[patent_app_country] => US
[patent_app_date] => 1998-05-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/333/06333528.pdf
[firstpage_image] =>[orig_patent_app_number] => 071795
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/071795 | Semiconductor device having a capacitor exhibiting improved moisture resistance | May 3, 1998 | Issued |
Array
(
[id] => 4366257
[patent_doc_number] => 06255701
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Semiconductor device containing local interconnection and method of manufacturing the same'
[patent_app_type] => 1
[patent_app_number] => 9/070235
[patent_app_country] => US
[patent_app_date] => 1998-04-30
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[firstpage_image] =>[orig_patent_app_number] => 070235
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/070235 | Semiconductor device containing local interconnection and method of manufacturing the same | Apr 29, 1998 | Issued |
Array
(
[id] => 4222453
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[patent_kind] => NA
[patent_issue_date] => 2000-08-29
[patent_title] => 'Interconnection with integrated corrosion stop'
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[patent_app_number] => 9/066121
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[patent_app_date] => 1998-04-24
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[pdf_file] => patents/06/111/06111301.pdf
[firstpage_image] =>[orig_patent_app_number] => 066121
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/066121 | Interconnection with integrated corrosion stop | Apr 23, 1998 | Issued |
Array
(
[id] => 1197804
[patent_doc_number] => 06727569
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-27
[patent_title] => 'Method of making enhanced trench oxide with low temperature nitrogen integration'
[patent_app_type] => B1
[patent_app_number] => 09/063081
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[patent_app_date] => 1998-04-21
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[pdf_file] => patents/06/727/06727569.pdf
[firstpage_image] =>[orig_patent_app_number] => 09063081
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/063081 | Method of making enhanced trench oxide with low temperature nitrogen integration | Apr 20, 1998 | Issued |
Array
(
[id] => 5782870
[patent_doc_number] => 20020158312
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-31
[patent_title] => 'DEVICES WITH PATTERNED WELLS AND METHOD FOR FORMING SAME'
[patent_app_type] => new
[patent_app_number] => 09/062964
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[firstpage_image] =>[orig_patent_app_number] => 09062964
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/062964 | Device with patterned wells and method for forming same | Apr 19, 1998 | Issued |
Array
(
[id] => 4089455
[patent_doc_number] => 06163048
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-19
[patent_title] => 'Semiconductor non-volatile memory device having a NAND cell structure'
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[patent_app_country] => US
[patent_app_date] => 1998-04-16
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[pdf_file] => patents/06/163/06163048.pdf
[firstpage_image] =>[orig_patent_app_number] => 051700
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/051700 | Semiconductor non-volatile memory device having a NAND cell structure | Apr 15, 1998 | Issued |