Search

Nanda Bondade

Examiner (ID: 16161)

Most Active Art Unit
2912
Art Unit(s)
2912, 2900, 2902
Total Applications
5029
Issued Applications
4983
Pending Applications
0
Abandoned Applications
46

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4209556 [patent_doc_number] => 06078057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-20 [patent_title] => 'Semiconductor devices having backside probing capability' [patent_app_type] => 1 [patent_app_number] => 9/010881 [patent_app_country] => US [patent_app_date] => 1998-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2155 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/078/06078057.pdf [firstpage_image] =>[orig_patent_app_number] => 010881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/010881
Semiconductor devices having backside probing capability Jan 21, 1998 Issued
Array ( [id] => 4089697 [patent_doc_number] => 06163065 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-19 [patent_title] => 'Energy-absorbing stable guard ring' [patent_app_type] => 1 [patent_app_number] => 9/002116 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2611 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/163/06163065.pdf [firstpage_image] =>[orig_patent_app_number] => 002116 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/002116
Energy-absorbing stable guard ring Dec 30, 1997 Issued
Array ( [id] => 4139675 [patent_doc_number] => 06121655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/000848 [patent_app_country] => US [patent_app_date] => 1997-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 42 [patent_no_of_words] => 15358 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/121/06121655.pdf [firstpage_image] =>[orig_patent_app_number] => 000848 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/000848
Nonvolatile semiconductor memory device and method for fabricating the same and semiconductor integrated circuit Dec 29, 1997 Issued
Array ( [id] => 1587917 [patent_doc_number] => 06359331 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-19 [patent_title] => 'High power switching module' [patent_app_type] => B1 [patent_app_number] => 08/997220 [patent_app_country] => US [patent_app_date] => 1997-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 2392 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/359/06359331.pdf [firstpage_image] =>[orig_patent_app_number] => 08997220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/997220
High power switching module Dec 22, 1997 Issued
Array ( [id] => 4292325 [patent_doc_number] => 06268623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Apparatus and method for margin testing single polysilicon EEPROM cells' [patent_app_type] => 1 [patent_app_number] => 8/995873 [patent_app_country] => US [patent_app_date] => 1997-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 25 [patent_no_of_words] => 9834 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/268/06268623.pdf [firstpage_image] =>[orig_patent_app_number] => 995873 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/995873
Apparatus and method for margin testing single polysilicon EEPROM cells Dec 21, 1997 Issued
Array ( [id] => 4176756 [patent_doc_number] => 06140691 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-31 [patent_title] => 'Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate' [patent_app_type] => 1 [patent_app_number] => 8/994701 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 17 [patent_no_of_words] => 4743 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/140/06140691.pdf [firstpage_image] =>[orig_patent_app_number] => 994701 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/994701
Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate Dec 18, 1997 Issued
08/989822 HIGH DENSITY ISOLATION USING AN IMPLANT AS A POLISH STOP Dec 11, 1997 Abandoned
Array ( [id] => 3918200 [patent_doc_number] => 06002160 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Semiconductor isolation process to minimize weak oxide problems' [patent_app_type] => 1 [patent_app_number] => 8/989820 [patent_app_country] => US [patent_app_date] => 1997-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2547 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/002/06002160.pdf [firstpage_image] =>[orig_patent_app_number] => 989820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/989820
Semiconductor isolation process to minimize weak oxide problems Dec 11, 1997 Issued
08/990141 SYMMETRICALLY IMPLANTED PUNCH-THROUGH STOPPER FOR RUGGED DMOS POWER DEVICE STRUCTURE AND METHOD OF MAKING SAME Dec 11, 1997 Abandoned
Array ( [id] => 4244166 [patent_doc_number] => 06091126 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Electromagnetic wave detector' [patent_app_type] => 1 [patent_app_number] => 8/984944 [patent_app_country] => US [patent_app_date] => 1997-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2089 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/091/06091126.pdf [firstpage_image] =>[orig_patent_app_number] => 984944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/984944
Electromagnetic wave detector Dec 3, 1997 Issued
Array ( [id] => 3933023 [patent_doc_number] => 05877529 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness' [patent_app_type] => 1 [patent_app_number] => 8/978667 [patent_app_country] => US [patent_app_date] => 1997-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 4383 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877529.pdf [firstpage_image] =>[orig_patent_app_number] => 978667 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/978667
Mosfet termination design and core cell configuration to increase breakdown voltage and to improve device ruggedness Nov 25, 1997 Issued
Array ( [id] => 4294014 [patent_doc_number] => 06211547 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Semiconductor memory array with buried drain lines and processing methods therefor' [patent_app_type] => 1 [patent_app_number] => 8/976751 [patent_app_country] => US [patent_app_date] => 1997-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 7705 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/211/06211547.pdf [firstpage_image] =>[orig_patent_app_number] => 976751 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/976751
Semiconductor memory array with buried drain lines and processing methods therefor Nov 23, 1997 Issued
Array ( [id] => 4389928 [patent_doc_number] => 06262466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-17 [patent_title] => 'Lateral semiconductor structure for forming a temperature-compensated voltage limitation' [patent_app_type] => 1 [patent_app_number] => 8/968003 [patent_app_country] => US [patent_app_date] => 1997-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2903 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/262/06262466.pdf [firstpage_image] =>[orig_patent_app_number] => 968003 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/968003
Lateral semiconductor structure for forming a temperature-compensated voltage limitation Nov 11, 1997 Issued
Array ( [id] => 3990162 [patent_doc_number] => 05910664 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Emitter-switched transistor structures' [patent_app_type] => 1 [patent_app_number] => 8/964868 [patent_app_country] => US [patent_app_date] => 1997-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3307 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 335 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/910/05910664.pdf [firstpage_image] =>[orig_patent_app_number] => 964868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/964868
Emitter-switched transistor structures Nov 4, 1997 Issued
Array ( [id] => 4179673 [patent_doc_number] => 06084268 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Power MOSFET device having low on-resistance and method' [patent_app_type] => 1 [patent_app_number] => 8/962725 [patent_app_country] => US [patent_app_date] => 1997-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 3763 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084268.pdf [firstpage_image] =>[orig_patent_app_number] => 962725 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962725
Power MOSFET device having low on-resistance and method Nov 2, 1997 Issued
Array ( [id] => 1571142 [patent_doc_number] => 06498366 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-24 [patent_title] => 'Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode' [patent_app_type] => B1 [patent_app_number] => 08/962322 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 17 [patent_no_of_words] => 3605 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/498/06498366.pdf [firstpage_image] =>[orig_patent_app_number] => 08962322 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962322
Semiconductor device that exhibits decreased contact resistance between substrate and drain electrode Oct 30, 1997 Issued
Array ( [id] => 4203535 [patent_doc_number] => 06013939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-11 [patent_title] => 'Monolithic inductor with magnetic flux lines guided away from substrate' [patent_app_type] => 1 [patent_app_number] => 8/962377 [patent_app_country] => US [patent_app_date] => 1997-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 4782 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/013/06013939.pdf [firstpage_image] =>[orig_patent_app_number] => 962377 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/962377
Monolithic inductor with magnetic flux lines guided away from substrate Oct 30, 1997 Issued
Array ( [id] => 3812490 [patent_doc_number] => 05831319 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-03 [patent_title] => 'Conductive spacer lightly doped drain (LDD) for hot carrier effect (HCE) control' [patent_app_type] => 1 [patent_app_number] => 8/954820 [patent_app_country] => US [patent_app_date] => 1997-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4576 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/831/05831319.pdf [firstpage_image] =>[orig_patent_app_number] => 954820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/954820
Conductive spacer lightly doped drain (LDD) for hot carrier effect (HCE) control Oct 20, 1997 Issued
Array ( [id] => 4137551 [patent_doc_number] => 06147382 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-14 [patent_title] => 'Semiconductor switching device with segmented sources' [patent_app_type] => 1 [patent_app_number] => 8/953050 [patent_app_country] => US [patent_app_date] => 1997-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 4022 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/147/06147382.pdf [firstpage_image] =>[orig_patent_app_number] => 953050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/953050
Semiconductor switching device with segmented sources Oct 16, 1997 Issued
08/949504 APPARATUS AND METHOD OF FABRICATING INVERSION CHANNEL DEVICES WITH PRECISION GATE DOPING FOR A MONOLITHIC INTERGRATED CIRCUIT Oct 13, 1997 Abandoned
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