
Nanda Bondade
Examiner (ID: 16161)
| Most Active Art Unit | 2912 |
| Art Unit(s) | 2912, 2900, 2902 |
| Total Applications | 5029 |
| Issued Applications | 4983 |
| Pending Applications | 0 |
| Abandoned Applications | 46 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 3940240
[patent_doc_number] => 05929485
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'High voltage insulated gate type bipolar transistor for self-isolated smart power IC'
[patent_app_type] => 1
[patent_app_number] => 8/824318
[patent_app_country] => US
[patent_app_date] => 1997-03-26
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/929/05929485.pdf
[firstpage_image] =>[orig_patent_app_number] => 824318
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/824318 | High voltage insulated gate type bipolar transistor for self-isolated smart power IC | Mar 25, 1997 | Issued |
Array
(
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[patent_doc_number] => 05990525
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'ROM device structure comprised of ROM memory array cells, featuring concave channel regions'
[patent_app_type] => 1
[patent_app_number] => 8/822666
[patent_app_country] => US
[patent_app_date] => 1997-03-24
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[pdf_file] => patents/05/990/05990525.pdf
[firstpage_image] =>[orig_patent_app_number] => 822666
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/822666 | ROM device structure comprised of ROM memory array cells, featuring concave channel regions | Mar 23, 1997 | Issued |
Array
(
[id] => 4026840
[patent_doc_number] => 05925901
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-20
[patent_title] => 'Field effect transistor with plated heat sink on a fet chip'
[patent_app_type] => 1
[patent_app_number] => 8/824020
[patent_app_country] => US
[patent_app_date] => 1997-03-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/824020 | Field effect transistor with plated heat sink on a fet chip | Mar 20, 1997 | Issued |
Array
(
[id] => 4139763
[patent_doc_number] => 06121661
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[patent_kind] => NA
[patent_issue_date] => 2000-09-19
[patent_title] => 'Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation'
[patent_app_type] => 1
[patent_app_number] => 8/822440
[patent_app_country] => US
[patent_app_date] => 1997-03-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/822440 | Silicon-on-insulator structure for electrostatic discharge protection and improved heat dissipation | Mar 20, 1997 | Issued |
Array
(
[id] => 4108441
[patent_doc_number] => 06100572
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[patent_kind] => NA
[patent_issue_date] => 2000-08-08
[patent_title] => 'Amorphous silicon combined with resurf region for termination for MOSgated device'
[patent_app_type] => 1
[patent_app_number] => 8/822398
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Array
(
[id] => 3953734
[patent_doc_number] => 05977591
[patent_country] => US
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[patent_issue_date] => 1999-11-02
[patent_title] => 'High-voltage-resistant MOS transistor, and corresponding manufacturing process'
[patent_app_type] => 1
[patent_app_number] => 8/824888
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Array
(
[id] => 4297576
[patent_doc_number] => 06236099
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[patent_issue_date] => 2001-05-22
[patent_title] => 'Trench MOS device and process for radhard device'
[patent_app_type] => 1
[patent_app_number] => 8/818908
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/818908 | Trench MOS device and process for radhard device | Mar 16, 1997 | Issued |
Array
(
[id] => 3799553
[patent_doc_number] => 05780907
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-14
[patent_title] => 'Semiconductor device having triple wells'
[patent_app_type] => 1
[patent_app_number] => 8/819488
[patent_app_country] => US
[patent_app_date] => 1997-03-17
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 819488
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/819488 | Semiconductor device having triple wells | Mar 16, 1997 | Issued |
Array
(
[id] => 3880253
[patent_doc_number] => 05825077
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-20
[patent_title] => 'Interconnect decoupling scheme'
[patent_app_type] => 1
[patent_app_number] => 8/815764
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[patent_app_date] => 1997-03-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/815764 | Interconnect decoupling scheme | Mar 11, 1997 | Issued |
Array
(
[id] => 3985188
[patent_doc_number] => 05949133
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[patent_issue_date] => 1999-09-07
[patent_title] => 'Semiconductor interconnect structure for high temperature applications'
[patent_app_type] => 1
[patent_app_number] => 8/815546
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[patent_app_date] => 1997-03-12
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/815546 | Semiconductor interconnect structure for high temperature applications | Mar 11, 1997 | Issued |
Array
(
[id] => 3896032
[patent_doc_number] => 05834816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-11-10
[patent_title] => 'MOSFET having tapered gate electrode'
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[patent_app_number] => 8/816009
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[pdf_file] => patents/05/834/05834816.pdf
[firstpage_image] =>[orig_patent_app_number] => 816009
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/816009 | MOSFET having tapered gate electrode | Mar 9, 1997 | Issued |
Array
(
[id] => 4212135
[patent_doc_number] => 06028324
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[patent_issue_date] => 2000-02-22
[patent_title] => 'Test structures for monitoring gate oxide defect densities and the plasma antenna effect'
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Array
(
[id] => 4136943
[patent_doc_number] => 06034399
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[patent_issue_date] => 2000-03-07
[patent_title] => 'Electrostatic discharge protection for silicon-on-insulator'
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[patent_app_number] => 8/812183
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Array
(
[id] => 4026760
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[patent_title] => 'Silicon carbide power MESFET with surface effect supressive layer'
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Array
(
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[patent_title] => 'Low dosage field rings for high voltage semiconductor device'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/812848 | Low dosage field rings for high voltage semiconductor device | Mar 5, 1997 | Issued |
Array
(
[id] => 1587739
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[patent_title] => 'Insulator-compound semiconductor interface structure'
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Array
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Array
(
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[patent_title] => 'BIPOLAR TRANSISTOR HAVING LIGHTLY DOPED EPITAXIAL COLLECTOR REGION CONSTANT IN DOPANT IMPURITY AND PROCESS OF FABRICATION THEREOF'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/806422 | Transistor having main cell and sub-cells | Feb 25, 1997 | Issued |