
Nanda Bondade
Examiner (ID: 16161)
| Most Active Art Unit | 2912 |
| Art Unit(s) | 2912, 2900, 2902 |
| Total Applications | 5029 |
| Issued Applications | 4983 |
| Pending Applications | 0 |
| Abandoned Applications | 46 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4227616
[patent_doc_number] => 06011291
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-01-04
[patent_title] => 'Video display with integrated control circuitry formed on a dielectric substrate'
[patent_app_type] => 1
[patent_app_number] => 8/803933
[patent_app_country] => US
[patent_app_date] => 1997-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 13
[patent_no_of_words] => 2275
[patent_no_of_claims] => 19
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[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/011/06011291.pdf
[firstpage_image] =>[orig_patent_app_number] => 803933
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/803933 | Video display with integrated control circuitry formed on a dielectric substrate | Feb 20, 1997 | Issued |
Array
(
[id] => 4120072
[patent_doc_number] => 06046491
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-04-04
[patent_title] => 'Semiconductor resistor element having improved resistance tolerance and semiconductor device therefor'
[patent_app_type] => 1
[patent_app_number] => 8/802314
[patent_app_country] => US
[patent_app_date] => 1997-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[patent_no_of_words] => 8863
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[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 340
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/046/06046491.pdf
[firstpage_image] =>[orig_patent_app_number] => 802314
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/802314 | Semiconductor resistor element having improved resistance tolerance and semiconductor device therefor | Feb 17, 1997 | Issued |
Array
(
[id] => 3820554
[patent_doc_number] => 05789782
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Lateral semiconductor device with maximized breakdown voltage, and methods of fixing potential of same'
[patent_app_type] => 1
[patent_app_number] => 8/794146
[patent_app_country] => US
[patent_app_date] => 1997-02-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4076
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[patent_words_short_claim] => 134
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[pdf_file] => patents/05/789/05789782.pdf
[firstpage_image] =>[orig_patent_app_number] => 794146
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/794146 | Lateral semiconductor device with maximized breakdown voltage, and methods of fixing potential of same | Feb 2, 1997 | Issued |
Array
(
[id] => 3984840
[patent_doc_number] => 05949109
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-07
[patent_title] => 'Semiconductor device having input protection circuit'
[patent_app_type] => 1
[patent_app_number] => 8/790804
[patent_app_country] => US
[patent_app_date] => 1997-01-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 17
[patent_no_of_words] => 4527
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 10
[patent_words_short_claim] => 128
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[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/949/05949109.pdf
[firstpage_image] =>[orig_patent_app_number] => 790804
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/790804 | Semiconductor device having input protection circuit | Jan 29, 1997 | Issued |
Array
(
[id] => 3766601
[patent_doc_number] => 05844284
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-12-01
[patent_title] => 'Damage free buried contact using salicide technology'
[patent_app_type] => 1
[patent_app_number] => 8/787589
[patent_app_country] => US
[patent_app_date] => 1997-01-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 2803
[patent_no_of_claims] => 9
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[pdf_file] => patents/05/844/05844284.pdf
[firstpage_image] =>[orig_patent_app_number] => 787589
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/787589 | Damage free buried contact using salicide technology | Jan 21, 1997 | Issued |
Array
(
[id] => 3980588
[patent_doc_number] => 05917220
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-06-29
[patent_title] => 'Integrated circuit with improved overvoltage protection'
[patent_app_type] => 1
[patent_app_number] => 8/777784
[patent_app_country] => US
[patent_app_date] => 1996-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 8
[patent_no_of_words] => 6676
[patent_no_of_claims] => 23
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[pdf_file] => patents/05/917/05917220.pdf
[firstpage_image] =>[orig_patent_app_number] => 777784
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/777784 | Integrated circuit with improved overvoltage protection | Dec 30, 1996 | Issued |
Array
(
[id] => 3745330
[patent_doc_number] => 05753955
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-05-19
[patent_title] => 'MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates'
[patent_app_type] => 1
[patent_app_number] => 8/770616
[patent_app_country] => US
[patent_app_date] => 1996-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 1821
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/753/05753955.pdf
[firstpage_image] =>[orig_patent_app_number] => 770616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/770616 | MOS device having a gate to body connection with a body injection current limiting feature for use on silicon on insulator substrates | Dec 18, 1996 | Issued |
Array
(
[id] => 5948568
[patent_doc_number] => 20020005555
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-01-17
[patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING A SILICON BODY WITH BIPOLAR AND MOS TRANSISTORS'
[patent_app_type] => new
[patent_app_number] => 08/768488
[patent_app_country] => US
[patent_app_date] => 1996-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2024
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0005/20020005555.pdf
[firstpage_image] =>[orig_patent_app_number] => 08768488
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768488 | SEMICONDUCTOR DEVICE COMPRISING A SILICON BODY WITH BIPOLAR AND MOS TRANSISTORS | Dec 17, 1996 | Abandoned |
Array
(
[id] => 3892597
[patent_doc_number] => 05777373
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-07-07
[patent_title] => 'Semiconductor structure with field-limiting rings and method for making'
[patent_app_type] => 1
[patent_app_number] => 8/767438
[patent_app_country] => US
[patent_app_date] => 1996-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2220
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
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[pdf_file] => patents/05/777/05777373.pdf
[firstpage_image] =>[orig_patent_app_number] => 767438
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/767438 | Semiconductor structure with field-limiting rings and method for making | Dec 15, 1996 | Issued |
Array
(
[id] => 3918099
[patent_doc_number] => 06002153
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-12-14
[patent_title] => 'MOS type semiconductor device with a current detecting function'
[patent_app_type] => 1
[patent_app_number] => 8/760806
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 4903
[patent_no_of_claims] => 13
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[pdf_file] => patents/06/002/06002153.pdf
[firstpage_image] =>[orig_patent_app_number] => 760806
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/760806 | MOS type semiconductor device with a current detecting function | Dec 4, 1996 | Issued |
Array
(
[id] => 3892169
[patent_doc_number] => 05894154
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-13
[patent_title] => 'P-channel MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/761052
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[patent_no_of_words] => 2932
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[pdf_file] => patents/05/894/05894154.pdf
[firstpage_image] =>[orig_patent_app_number] => 761052
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/761052 | P-channel MOS transistor | Dec 4, 1996 | Issued |
Array
(
[id] => 3801572
[patent_doc_number] => 05828081
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-10-27
[patent_title] => 'Integrated semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/759177
[patent_app_country] => US
[patent_app_date] => 1996-12-04
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/828/05828081.pdf
[firstpage_image] =>[orig_patent_app_number] => 759177
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759177 | Integrated semiconductor device | Dec 3, 1996 | Issued |
Array
(
[id] => 3882644
[patent_doc_number] => 05804856
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-08
[patent_title] => 'Depleted sidewall-poly LDD transistor'
[patent_app_type] => 1
[patent_app_number] => 8/753616
[patent_app_country] => US
[patent_app_date] => 1996-11-27
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/804/05804856.pdf
[firstpage_image] =>[orig_patent_app_number] => 753616
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/753616 | Depleted sidewall-poly LDD transistor | Nov 26, 1996 | Issued |
Array
(
[id] => 3820640
[patent_doc_number] => 05789788
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Semiconductor device with first and second wells which have opposite conductivity types and a third well region formed on one of the first and second wells'
[patent_app_type] => 1
[patent_app_number] => 8/754615
[patent_app_country] => US
[patent_app_date] => 1996-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/789/05789788.pdf
[firstpage_image] =>[orig_patent_app_number] => 754615
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/754615 | Semiconductor device with first and second wells which have opposite conductivity types and a third well region formed on one of the first and second wells | Nov 19, 1996 | Issued |
Array
(
[id] => 3879135
[patent_doc_number] => 05763926
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-06-09
[patent_title] => 'Semiconductor device having a Bi-CMOS transistor including an n-channel MOS transistor'
[patent_app_type] => 1
[patent_app_number] => 8/742120
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/763/05763926.pdf
[firstpage_image] =>[orig_patent_app_number] => 742120
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/742120 | Semiconductor device having a Bi-CMOS transistor including an n-channel MOS transistor | Oct 30, 1996 | Issued |
| 08/734084 | SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME | Oct 20, 1996 | Abandoned |
Array
(
[id] => 4069992
[patent_doc_number] => 05866932
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-02
[patent_title] => 'Insulating film formed using an organic silane and method of producing semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/734127
[patent_app_country] => US
[patent_app_date] => 1996-10-21
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/866/05866932.pdf
[firstpage_image] =>[orig_patent_app_number] => 734127
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/734127 | Insulating film formed using an organic silane and method of producing semiconductor device | Oct 20, 1996 | Issued |
Array
(
[id] => 3692413
[patent_doc_number] => 05696396
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-12-09
[patent_title] => 'Semiconductor device including vertical MOSFET structure with suppressed parasitic diode operation'
[patent_app_type] => 1
[patent_app_number] => 8/734132
[patent_app_country] => US
[patent_app_date] => 1996-10-21
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[rel_patent_id] =>[rel_patent_doc_number] =>) 08/734132 | Semiconductor device including vertical MOSFET structure with suppressed parasitic diode operation | Oct 20, 1996 | Issued |
Array
(
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Array
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