Nanda Bondade

Array ( [id] => 3661963 [patent_doc_number] => 05659190 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-19 [patent_title] => 'Semiconductor device in a thin active layer with high breakdown voltage' [patent_app_type] => 1 [patent_app_number] => 8/669848 [patent_app_country] => US [patent_app_date] => 1996-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 26 [patent_no_of_words] => 7446 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 451 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/659/05659190.pdf [firstpage_image] =>[orig_patent_app_number] => 669848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7639838 [patent_doc_number] => 06396078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-28 [patent_title] => 'Semiconductor device with a tapered hole formed using multiple layers with different etching rates' [patent_app_type] => B1 [patent_app_number] => 08/666104 [patent_app_country] => US [patent_app_date] => 1996-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 25 [patent_no_of_words] => 7268 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/396/06396078.pdf [firstpage_image] =>[orig_patent_app_number] => 08666104 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3665076 [patent_doc_number] => 05656843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Semiconductor device having a vertical insulated gate field effect device and a breakdown region remote from the gate' [patent_app_type] => 1 [patent_app_number] => 8/668426 [patent_app_country] => US [patent_app_date] => 1996-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 5087 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/656/05656843.pdf [firstpage_image] =>[orig_patent_app_number] => 668426 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3950608 [patent_doc_number] => RE036314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-28 [patent_title] => 'Insulated gate field effect semiconductor devices having a LDD region and an anodic oxide film of a gate electrode' [patent_app_type] => 2 [patent_app_number] => 8/620857 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 8907 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/RE/036/RE036314.pdf [firstpage_image] =>[orig_patent_app_number] => 620857 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3938876 [patent_doc_number] => 05939755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Power IC having high-side and low-side switches in an SOI structure' [patent_app_type] => 1 [patent_app_number] => 8/655600 [patent_app_country] => US [patent_app_date] => 1996-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 9342 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939755.pdf [firstpage_image] =>[orig_patent_app_number] => 655600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3740917 [patent_doc_number] => 05698883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'MOS field effect transistor and method for manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/654754 [patent_app_country] => US [patent_app_date] => 1996-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 3545 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/698/05698883.pdf [firstpage_image] =>[orig_patent_app_number] => 654754 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3857590 [patent_doc_number] => 05767557 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-16 [patent_title] => 'PMOSFETS having indium or gallium doped buried channels and n+polysilicon gates and CMOS devices fabricated therefrom' [patent_app_type] => 1 [patent_app_number] => 8/656996 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 2755 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/767/05767557.pdf [firstpage_image] =>[orig_patent_app_number] => 656996 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4003172 [patent_doc_number] => 05986340 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Ball grid array package with enhanced thermal and electrical characteristics and electronic device incorporating same' [patent_app_type] => 1 [patent_app_number] => 8/641933 [patent_app_country] => US [patent_app_date] => 1996-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3588 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/986/05986340.pdf [firstpage_image] =>[orig_patent_app_number] => 641933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3885541 [patent_doc_number] => 05798549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-25 [patent_title] => 'Conductive layer overlaid self-aligned MOS-gated semiconductor devices' [patent_app_type] => 1 [patent_app_number] => 8/649956 [patent_app_country] => US [patent_app_date] => 1996-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 46 [patent_no_of_words] => 5930 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/798/05798549.pdf [firstpage_image] =>[orig_patent_app_number] => 649956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3766570 [patent_doc_number] => 05852314 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-22 [patent_title] => 'Thin epitaxy resurf integrated circuit containing high voltage p-channel and n-channel devices with source or drain not tied to ground' [patent_app_type] => 1 [patent_app_number] => 8/643152 [patent_app_country] => US [patent_app_date] => 1996-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2729 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/852/05852314.pdf [firstpage_image] =>[orig_patent_app_number] => 643152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3633230 [patent_doc_number] => 05686750 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-11 [patent_title] => 'Power semiconductor device having improved reverse recovery voltage' [patent_app_type] => 1 [patent_app_number] => 8/639433 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3204 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 570 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/686/05686750.pdf [firstpage_image] =>[orig_patent_app_number] => 639433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3776030 [patent_doc_number] => 05773871 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-30 [patent_title] => 'Integrated circuit structure and method of fabrication thereof' [patent_app_type] => 1 [patent_app_number] => 8/638084 [patent_app_country] => US [patent_app_date] => 1996-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 27 [patent_no_of_words] => 6060 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/773/05773871.pdf [firstpage_image] =>[orig_patent_app_number] => 638084 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3861987 [patent_doc_number] => 05705840 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Field effect transistor with recessed buried source and drain regions' [patent_app_type] => 1 [patent_app_number] => 8/636785 [patent_app_country] => US [patent_app_date] => 1996-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3161 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 314 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/705/05705840.pdf [firstpage_image] =>[orig_patent_app_number] => 636785 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4361128 [patent_doc_number] => 06201281 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Semiconductor device and method for producing the same' [patent_app_type] => 1 [patent_app_number] => 8/635283 [patent_app_country] => US [patent_app_date] => 1996-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2301 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/201/06201281.pdf [firstpage_image] =>[orig_patent_app_number] => 635283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4067700 [patent_doc_number] => 05895951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches' [patent_app_type] => 1 [patent_app_number] => 8/628493 [patent_app_country] => US [patent_app_date] => 1996-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 22 [patent_no_of_words] => 4029 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895951.pdf [firstpage_image] =>[orig_patent_app_number] => 628493 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3820565 [patent_doc_number] => 05789783 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-08-04 [patent_title] => 'Multilevel metallization structure for integrated circuit I/O lines for increased current capacity and ESD protection' [patent_app_type] => 1 [patent_app_number] => 8/626776 [patent_app_country] => US [patent_app_date] => 1996-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/789/05789783.pdf [firstpage_image] =>[orig_patent_app_number] => 626776 [rel_patent_id] =>[rel_patent_doc_number] =>)