| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3561265
[patent_doc_number] => 05525542
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-06-11
[patent_title] => 'Method for making a semiconductor device having anti-reflective coating'
[patent_app_type] => 1
[patent_app_number] => 8/393781
[patent_app_country] => US
[patent_app_date] => 1995-02-24
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[pdf_file] => patents/05/525/05525542.pdf
[firstpage_image] =>[orig_patent_app_number] => 393781
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/393781 | Method for making a semiconductor device having anti-reflective coating | Feb 23, 1995 | Issued |
Array
(
[id] => 3546968
[patent_doc_number] => 05545592
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-13
[patent_title] => 'Nitrogen treatment for metal-silicide contact'
[patent_app_type] => 1
[patent_app_number] => 8/393635
[patent_app_country] => US
[patent_app_date] => 1995-02-24
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[firstpage_image] =>[orig_patent_app_number] => 393635
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/393635 | Nitrogen treatment for metal-silicide contact | Feb 23, 1995 | Issued |
Array
(
[id] => 3581661
[patent_doc_number] => 05580821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-03
[patent_title] => 'Semiconductor processing method of forming an electrically conductive contact plug'
[patent_app_type] => 1
[patent_app_number] => 8/391719
[patent_app_country] => US
[patent_app_date] => 1995-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_words_short_claim] => 199
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[pdf_file] => patents/05/580/05580821.pdf
[firstpage_image] =>[orig_patent_app_number] => 391719
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/391719 | Semiconductor processing method of forming an electrically conductive contact plug | Feb 20, 1995 | Issued |
Array
(
[id] => 3620599
[patent_doc_number] => 05641708
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-06-24
[patent_title] => 'Method for fabricating conductive structures in integrated circuits'
[patent_app_type] => 1
[patent_app_number] => 8/387243
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[pdf_file] => patents/05/641/05641708.pdf
[firstpage_image] =>[orig_patent_app_number] => 387243
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387243 | Method for fabricating conductive structures in integrated circuits | Feb 12, 1995 | Issued |
Array
(
[id] => 3549764
[patent_doc_number] => 05547896
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-20
[patent_title] => 'Direct etch for thin film resistor using a hard mask'
[patent_app_type] => 1
[patent_app_number] => 8/387233
[patent_app_country] => US
[patent_app_date] => 1995-02-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 2015
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[pdf_file] => patents/05/547/05547896.pdf
[firstpage_image] =>[orig_patent_app_number] => 387233
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/387233 | Direct etch for thin film resistor using a hard mask | Feb 12, 1995 | Issued |
Array
(
[id] => 3611569
[patent_doc_number] => 05565379
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Method of manufacturing a semiconductor device having a bump electrode by a proximity exposure method'
[patent_app_type] => 1
[patent_app_number] => 8/386407
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[patent_app_date] => 1995-02-10
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[firstpage_image] =>[orig_patent_app_number] => 386407
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/386407 | Method of manufacturing a semiconductor device having a bump electrode by a proximity exposure method | Feb 9, 1995 | Issued |
Array
(
[id] => 3622932
[patent_doc_number] => 05612253
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-03-18
[patent_title] => 'Method for forming ordered titanium nitride and titanium silicide upon a semiconductor wafer using a three-step anneal process'
[patent_app_type] => 1
[patent_app_number] => 8/382217
[patent_app_country] => US
[patent_app_date] => 1995-01-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/612/05612253.pdf
[firstpage_image] =>[orig_patent_app_number] => 382217
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/382217 | Method for forming ordered titanium nitride and titanium silicide upon a semiconductor wafer using a three-step anneal process | Jan 30, 1995 | Issued |
Array
(
[id] => 3730796
[patent_doc_number] => 05665618
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-09-09
[patent_title] => 'Method of forming an interband lateral resonant tunneling transistor with single narrow gate electrode'
[patent_app_type] => 1
[patent_app_number] => 8/379833
[patent_app_country] => US
[patent_app_date] => 1995-01-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[patent_no_of_words] => 3832
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/665/05665618.pdf
[firstpage_image] =>[orig_patent_app_number] => 379833
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/379833 | Method of forming an interband lateral resonant tunneling transistor with single narrow gate electrode | Jan 26, 1995 | Issued |
Array
(
[id] => 3582477
[patent_doc_number] => 05584890
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-17
[patent_title] => 'Methods of making multiple anode capacitors'
[patent_app_type] => 1
[patent_app_number] => 8/377750
[patent_app_country] => US
[patent_app_date] => 1995-01-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/584/05584890.pdf
[firstpage_image] =>[orig_patent_app_number] => 377750
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/377750 | Methods of making multiple anode capacitors | Jan 23, 1995 | Issued |
Array
(
[id] => 3529641
[patent_doc_number] => 05583073
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-10
[patent_title] => 'Method for producing electroless barrier layer and solder bump on chip'
[patent_app_type] => 1
[patent_app_number] => 8/368847
[patent_app_country] => US
[patent_app_date] => 1995-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 3004
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[pdf_file] => patents/05/583/05583073.pdf
[firstpage_image] =>[orig_patent_app_number] => 368847
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/368847 | Method for producing electroless barrier layer and solder bump on chip | Jan 4, 1995 | Issued |
| 08/367537 | METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE | Jan 2, 1995 | Abandoned |
Array
(
[id] => 3552130
[patent_doc_number] => 05492855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-02-20
[patent_title] => 'Method of dry etching platinum using sulfur containing gas'
[patent_app_type] => 1
[patent_app_number] => 8/364115
[patent_app_country] => US
[patent_app_date] => 1994-12-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
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[pdf_file] => patents/05/492/05492855.pdf
[firstpage_image] =>[orig_patent_app_number] => 364115
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/364115 | Method of dry etching platinum using sulfur containing gas | Dec 26, 1994 | Issued |
Array
(
[id] => 3613336
[patent_doc_number] => 05510292
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-04-23
[patent_title] => 'Manufacturing method for a semiconductor device having local interconnections'
[patent_app_type] => 1
[patent_app_number] => 8/363931
[patent_app_country] => US
[patent_app_date] => 1994-12-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/510/05510292.pdf
[firstpage_image] =>[orig_patent_app_number] => 363931
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/363931 | Manufacturing method for a semiconductor device having local interconnections | Dec 26, 1994 | Issued |
| 08/357313 | METHOD FOR FORMING A TUNGSTEN SILICIDE LAYER IN A SEMICONDUCTOR DEVICE | Dec 15, 1994 | Abandoned |
Array
(
[id] => 3509815
[patent_doc_number] => 05563100
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-08
[patent_title] => 'Fabrication method of semiconductor device with refractory metal silicide formation by removing native oxide in hydrogen'
[patent_app_type] => 1
[patent_app_number] => 8/357403
[patent_app_country] => US
[patent_app_date] => 1994-12-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/563/05563100.pdf
[firstpage_image] =>[orig_patent_app_number] => 357403
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/357403 | Fabrication method of semiconductor device with refractory metal silicide formation by removing native oxide in hydrogen | Dec 15, 1994 | Issued |
Array
(
[id] => 3589695
[patent_doc_number] => 05567650
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method of forming tapered plug-filled via in electrical interconnection'
[patent_app_type] => 1
[patent_app_number] => 8/356421
[patent_app_country] => US
[patent_app_date] => 1994-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 1714
[patent_no_of_claims] => 13
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[pdf_file] => patents/05/567/05567650.pdf
[firstpage_image] =>[orig_patent_app_number] => 356421
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/356421 | Method of forming tapered plug-filled via in electrical interconnection | Dec 14, 1994 | Issued |
| 08/356928 | DEPOSITION PROCESS FOR COATING OR FILLING RE-ENTRY SHAPED CONTACT HOLES | Dec 13, 1994 | Abandoned |
| 08/355625 | METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE | Dec 13, 1994 | Abandoned |
Array
(
[id] => 3554844
[patent_doc_number] => 05543357
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Process of manufacturing a semiconductor device by filling a via hole in an interlayered film of the device with wiring metal'
[patent_app_type] => 1
[patent_app_number] => 8/351679
[patent_app_country] => US
[patent_app_date] => 1994-12-08
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/543/05543357.pdf
[firstpage_image] =>[orig_patent_app_number] => 351679
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/351679 | Process of manufacturing a semiconductor device by filling a via hole in an interlayered film of the device with wiring metal | Dec 7, 1994 | Issued |
Array
(
[id] => 3589657
[patent_doc_number] => 05567647
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-22
[patent_title] => 'Method for fabricating a gate electrode structure of compound semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 8/354067
[patent_app_country] => US
[patent_app_date] => 1994-12-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/567/05567647.pdf
[firstpage_image] =>[orig_patent_app_number] => 354067
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/354067 | Method for fabricating a gate electrode structure of compound semiconductor device | Dec 5, 1994 | Issued |