Nasser Moazzami Goodarzi

Array ( [id] => 1580326 [patent_doc_number] => 06470423 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-22 [patent_title] => 'Managing partitioned cache' [patent_app_type] => B1 [patent_app_number] => 10/032243 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6815 [patent_no_of_claims] => 59 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/470/06470423.pdf [firstpage_image] =>[orig_patent_app_number] => 10032243 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 992691 [patent_doc_number] => 06920541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-19 [patent_title] => 'Trace termination for on-the-fly garbage collection for weakly-consistent computer architecture' [patent_app_type] => utility [patent_app_number] => 10/021424 [patent_app_country] => US [patent_app_date] => 2001-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3899 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/920/06920541.pdf [firstpage_image] =>[orig_patent_app_number] => 10021424 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1400922 [patent_doc_number] => 06564289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-13 [patent_title] => 'Method and apparatus for performing a read next highest priority match instruction in a content addressable memory device' [patent_app_type] => B2 [patent_app_number] => 10/025661 [patent_app_country] => US [patent_app_date] => 2001-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11837 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564289.pdf [firstpage_image] =>[orig_patent_app_number] => 10025661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7605799 [patent_doc_number] => 07099923 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-29 [patent_title] => 'Data storage system' [patent_app_type] => utility [patent_app_number] => 09/998995 [patent_app_country] => US [patent_app_date] => 2001-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6142 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/099/07099923.pdf [firstpage_image] =>[orig_patent_app_number] => 09998995 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 680051 [patent_doc_number] => 07089390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-08 [patent_title] => 'Apparatus and method to reduce memory footprints in processor architectures' [patent_app_type] => utility [patent_app_number] => 10/003563 [patent_app_country] => US [patent_app_date] => 2001-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 14144 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/089/07089390.pdf [firstpage_image] =>[orig_patent_app_number] => 10003563 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784235 [patent_doc_number] => 20030065683 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Data storage device and method for storing information using alternate information storage architectures' [patent_app_type] => new [patent_app_number] => 09/968592 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5072 [patent_no_of_claims] => 62 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065683.pdf [firstpage_image] =>[orig_patent_app_number] => 09968592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784219 [patent_doc_number] => 20030065667 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Data management system, method and apparatus for fast multiple file write operations' [patent_app_type] => new [patent_app_number] => 09/968590 [patent_app_country] => US [patent_app_date] => 2001-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 5576 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065667.pdf [firstpage_image] =>[orig_patent_app_number] => 09968590 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1248822 [patent_doc_number] => 06678785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Flash management system using only sequential write' [patent_app_type] => B2 [patent_app_number] => 09/964606 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4057 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678785.pdf [firstpage_image] =>[orig_patent_app_number] => 09964606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1214329 [patent_doc_number] => 06715027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Ranked cleaning policy and error recovery method for file systems using flash memory' [patent_app_type] => B2 [patent_app_number] => 09/967585 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5235 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715027.pdf [firstpage_image] =>[orig_patent_app_number] => 09967585 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1075090 [patent_doc_number] => 06839758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Network processor for cache array routing' [patent_app_type] => utility [patent_app_number] => 09/964804 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839758.pdf [firstpage_image] =>[orig_patent_app_number] => 09964804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5830431 [patent_doc_number] => 20020069315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Memory apparatus and memory access restricting method' [patent_app_type] => new [patent_app_number] => 09/967002 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3470 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069315.pdf [firstpage_image] =>[orig_patent_app_number] => 09967002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784436 [patent_doc_number] => 20030065884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Hiding refresh of memory and refresh-hidden memory' [patent_app_type] => new [patent_app_number] => 09/966586 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10463 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065884.pdf [firstpage_image] =>[orig_patent_app_number] => 09966586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6766914 [patent_doc_number] => 20030101314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Memory module resync' [patent_app_type] => new [patent_app_number] => 09/966892 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14533 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101314.pdf [firstpage_image] =>[orig_patent_app_number] => 09966892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6115317 [patent_doc_number] => 20020174293 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-21 [patent_title] => 'Parametric optimization of a disc drive through I/O command sequence analysis' [patent_app_type] => new [patent_app_number] => 09/966461 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5893 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20020174293.pdf [firstpage_image] =>[orig_patent_app_number] => 09966461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1100372 [patent_doc_number] => 06823424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-23 [patent_title] => 'Rebuild bus utilization' [patent_app_type] => B2 [patent_app_number] => 09/966666 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6491 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823424.pdf [firstpage_image] =>[orig_patent_app_number] => 09966666 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7622380 [patent_doc_number] => 06687786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Automated free entry management for content-addressable memory using virtual page pre-fetch' [patent_app_type] => B1 [patent_app_number] => 09/966059 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4999 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687786.pdf [firstpage_image] =>[orig_patent_app_number] => 09966059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6819097 [patent_doc_number] => 20030070055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Memory latency and bandwidth optimizations' [patent_app_type] => new [patent_app_number] => 09/965913 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9243 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070055.pdf [firstpage_image] =>[orig_patent_app_number] => 09965913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1139077 [patent_doc_number] => 06789180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method and apparatus for mask and/or counter address registers readback on the address bus in synchronous single and multi-port memories' [patent_app_type] => B1 [patent_app_number] => 09/966838 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6516 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789180.pdf [firstpage_image] =>[orig_patent_app_number] => 09966838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784444 [patent_doc_number] => 20030065892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Concurrent non-blocking FIFO array' [patent_app_type] => new [patent_app_number] => 09/966478 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9767 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065892.pdf [firstpage_image] =>[orig_patent_app_number] => 09966478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7613852 [patent_doc_number] => 06898679 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method and apparatus for reordering memory requests for page coherency' [patent_app_type] => utility [patent_app_number] => 09/968260 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2853 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898679.pdf [firstpage_image] =>[orig_patent_app_number] => 09968260 [rel_patent_id] =>[rel_patent_doc_number] =>)