Search

Nasser Moazzami Goodarzi

Supervisory Patent Examiner (ID: 12173, Phone: (571)272-4195 , Office: P/2426 )

Most Active Art Unit
2187
Art Unit(s)
2187, 2436, 2752, 2136, 2759, 2426
Total Applications
556
Issued Applications
479
Pending Applications
21
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6143541 [patent_doc_number] => 20020002657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Cache system for concurrent processes' [patent_app_type] => new [patent_app_number] => 09/924289 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6090 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20020002657.pdf [firstpage_image] =>[orig_patent_app_number] => 09924289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924289
Cache system for concurrent processes Aug 7, 2001 Issued
Array ( [id] => 6775515 [patent_doc_number] => 20030018853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Method and apparatus for filling lines in a cache' [patent_app_type] => new [patent_app_number] => 09/909562 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018853.pdf [firstpage_image] =>[orig_patent_app_number] => 09909562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909562
Method and apparatus for filling lines in a cache Jul 19, 2001 Issued
Array ( [id] => 1106215 [patent_doc_number] => 06816947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'System and method for memory arbitration' [patent_app_type] => B1 [patent_app_number] => 09/909705 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816947.pdf [firstpage_image] =>[orig_patent_app_number] => 09909705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909705
System and method for memory arbitration Jul 19, 2001 Issued
Array ( [id] => 6836102 [patent_doc_number] => 20030163648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Coherence-free cache' [patent_app_type] => new [patent_app_number] => 10/312117 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163648.pdf [firstpage_image] =>[orig_patent_app_number] => 10312117 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/312117
Coherence-free cache Jun 21, 2001 Issued
Array ( [id] => 6245279 [patent_doc_number] => 20020046297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'System containing a plurality of central processing units' [patent_app_type] => new [patent_app_number] => 09/886558 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5314 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046297.pdf [firstpage_image] =>[orig_patent_app_number] => 09886558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886558
System containing a plurality of central processing units Jun 20, 2001 Abandoned
Array ( [id] => 6332573 [patent_doc_number] => 20020198608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'System for addressing processors connected to a peripheral bus' [patent_app_type] => new [patent_app_number] => 09/886190 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3417 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20020198608.pdf [firstpage_image] =>[orig_patent_app_number] => 09886190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886190
System for addressing processors connected to a peripheral bus Jun 20, 2001 Issued
Array ( [id] => 1225645 [patent_doc_number] => 06704848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Apparatus for controlling time deinterleaver memory for digital audio broadcasting' [patent_app_type] => B2 [patent_app_number] => 09/866864 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4610 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704848.pdf [firstpage_image] =>[orig_patent_app_number] => 09866864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866864
Apparatus for controlling time deinterleaver memory for digital audio broadcasting May 29, 2001 Issued
Array ( [id] => 1431871 [patent_doc_number] => 06516383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Techniques for efficient location of free entries for TCAM inserts' [patent_app_type] => B1 [patent_app_number] => 09/871321 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5027 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516383.pdf [firstpage_image] =>[orig_patent_app_number] => 09871321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871321
Techniques for efficient location of free entries for TCAM inserts May 29, 2001 Issued
Array ( [id] => 1308950 [patent_doc_number] => 06629230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Host interface circuit' [patent_app_type] => B2 [patent_app_number] => 09/871144 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8648 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629230.pdf [firstpage_image] =>[orig_patent_app_number] => 09871144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871144
Host interface circuit May 29, 2001 Issued
Array ( [id] => 6424843 [patent_doc_number] => 20020184451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Unifying data storage in a distributed network' [patent_app_type] => new [patent_app_number] => 09/866735 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4631 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184451.pdf [firstpage_image] =>[orig_patent_app_number] => 09866735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866735
Unifying data storage in a distributed network May 29, 2001 Issued
Array ( [id] => 6424900 [patent_doc_number] => 20020184457 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Receiving apparatus that receives and accumulates broadcast contents and makes contents available according to user requests' [patent_app_type] => new [patent_app_number] => 09/867117 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 25016 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184457.pdf [firstpage_image] =>[orig_patent_app_number] => 09867117 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867117
Receiving apparatus that receives and accumulates broadcast contents and makes contents available according to user requests May 28, 2001 Issued
Array ( [id] => 6424847 [patent_doc_number] => 20020184452 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Embedded memory access method and system for application specific integrated circuits' [patent_app_type] => new [patent_app_number] => 09/867957 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3618 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184452.pdf [firstpage_image] =>[orig_patent_app_number] => 09867957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/867957
Embedded memory access method and system for application specific integrated circuits May 28, 2001 Issued
Array ( [id] => 6423455 [patent_doc_number] => 20020184328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Chip multiprocessor with multiple operating systems' [patent_app_type] => new [patent_app_number] => 09/865605 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1712 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184328.pdf [firstpage_image] =>[orig_patent_app_number] => 09865605 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865605
Chip multiprocessor with multiple operating systems May 28, 2001 Issued
Array ( [id] => 6424817 [patent_doc_number] => 20020184448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method for cache replacement of web documents' [patent_app_type] => new [patent_app_number] => 09/870060 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4222 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184448.pdf [firstpage_image] =>[orig_patent_app_number] => 09870060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870060
Method for cache replacement of web documents May 28, 2001 Issued
Array ( [id] => 6245409 [patent_doc_number] => 20020046332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Multi task information recordation system and information storage medium' [patent_app_type] => new [patent_app_number] => 09/865676 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5602 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046332.pdf [firstpage_image] =>[orig_patent_app_number] => 09865676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865676
Multi task information recordation system and information storage medium May 28, 2001 Issued
Array ( [id] => 6424651 [patent_doc_number] => 20020184437 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Memory architecture for supporting concurrent access of different types' [patent_app_type] => new [patent_app_number] => 09/870361 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2066 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184437.pdf [firstpage_image] =>[orig_patent_app_number] => 09870361 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870361
Memory architecture for supporting concurrent access of different types May 28, 2001 Issued
Array ( [id] => 5971433 [patent_doc_number] => 20020091901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-11 [patent_title] => 'Disk caching' [patent_app_type] => new [patent_app_number] => 09/866509 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20020091901.pdf [firstpage_image] =>[orig_patent_app_number] => 09866509 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866509
Method for caching information between work sessions May 24, 2001 Issued
Array ( [id] => 6460337 [patent_doc_number] => 20020178325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-11-28 [patent_title] => 'Method and apparatus for scalable error correction code generation performance' [patent_app_type] => new [patent_app_number] => 09/866110 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4515 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20020178325.pdf [firstpage_image] =>[orig_patent_app_number] => 09866110 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866110
Method and apparatus for scalable error correction code generation performance May 24, 2001 Issued
Array ( [id] => 1376907 [patent_doc_number] => 06578112 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-06-10 [patent_title] => 'Cache memory control device for multi-processor system' [patent_app_type] => B2 [patent_app_number] => 09/864328 [patent_app_country] => US [patent_app_date] => 2001-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 11509 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578112.pdf [firstpage_image] =>[orig_patent_app_number] => 09864328 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/864328
Cache memory control device for multi-processor system May 24, 2001 Issued
Array ( [id] => 999046 [patent_doc_number] => 06915396 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Fast priority determination circuit with rotating priority' [patent_app_type] => utility [patent_app_number] => 09/853738 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 8259 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/915/06915396.pdf [firstpage_image] =>[orig_patent_app_number] => 09853738 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/853738
Fast priority determination circuit with rotating priority May 9, 2001 Issued
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