Nasser Moazzami Goodarzi

Array ( [id] => 1075090 [patent_doc_number] => 06839758 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-04 [patent_title] => 'Network processor for cache array routing' [patent_app_type] => utility [patent_app_number] => 09/964804 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1566 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/839/06839758.pdf [firstpage_image] =>[orig_patent_app_number] => 09964804 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1139077 [patent_doc_number] => 06789180 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method and apparatus for mask and/or counter address registers readback on the address bus in synchronous single and multi-port memories' [patent_app_type] => B1 [patent_app_number] => 09/966838 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6516 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789180.pdf [firstpage_image] =>[orig_patent_app_number] => 09966838 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784436 [patent_doc_number] => 20030065884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Hiding refresh of memory and refresh-hidden memory' [patent_app_type] => new [patent_app_number] => 09/966586 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 10463 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065884.pdf [firstpage_image] =>[orig_patent_app_number] => 09966586 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1324048 [patent_doc_number] => 06611902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Information processor and information processing method' [patent_app_type] => B2 [patent_app_number] => 09/964604 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7208 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611902.pdf [firstpage_image] =>[orig_patent_app_number] => 09964604 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1248822 [patent_doc_number] => 06678785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-13 [patent_title] => 'Flash management system using only sequential write' [patent_app_type] => B2 [patent_app_number] => 09/964606 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4057 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678785.pdf [firstpage_image] =>[orig_patent_app_number] => 09964606 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6784444 [patent_doc_number] => 20030065892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-03 [patent_title] => 'Concurrent non-blocking FIFO array' [patent_app_type] => new [patent_app_number] => 09/966478 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 9767 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20030065892.pdf [firstpage_image] =>[orig_patent_app_number] => 09966478 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5830431 [patent_doc_number] => 20020069315 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Memory apparatus and memory access restricting method' [patent_app_type] => new [patent_app_number] => 09/967002 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3470 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0069/20020069315.pdf [firstpage_image] =>[orig_patent_app_number] => 09967002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6766914 [patent_doc_number] => 20030101314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Memory module resync' [patent_app_type] => new [patent_app_number] => 09/966892 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14533 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20030101314.pdf [firstpage_image] =>[orig_patent_app_number] => 09966892 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7622380 [patent_doc_number] => 06687786 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'Automated free entry management for content-addressable memory using virtual page pre-fetch' [patent_app_type] => B1 [patent_app_number] => 09/966059 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4999 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/687/06687786.pdf [firstpage_image] =>[orig_patent_app_number] => 09966059 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6819097 [patent_doc_number] => 20030070055 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Memory latency and bandwidth optimizations' [patent_app_type] => new [patent_app_number] => 09/965913 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 9243 [patent_no_of_claims] => 70 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20030070055.pdf [firstpage_image] =>[orig_patent_app_number] => 09965913 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6348810 [patent_doc_number] => 20020035663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'Method of validating data in circular buffers' [patent_app_type] => new [patent_app_number] => 09/950673 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2375 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20020035663.pdf [firstpage_image] =>[orig_patent_app_number] => 09950673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 785866 [patent_doc_number] => 06993566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Entity self-clustering and host-entity communication such as via shared memory' [patent_app_type] => utility [patent_app_number] => 09/952592 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5441 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993566.pdf [firstpage_image] =>[orig_patent_app_number] => 09952592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1353288 [patent_doc_number] => 06594739 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Memory system and method of using same' [patent_app_type] => B1 [patent_app_number] => 09/950546 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594739.pdf [firstpage_image] =>[orig_patent_app_number] => 09950546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7630004 [patent_doc_number] => 06636935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules' [patent_app_type] => B1 [patent_app_number] => 09/948755 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 18004 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636935.pdf [firstpage_image] =>[orig_patent_app_number] => 09948755 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1138905 [patent_doc_number] => 06789155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'System and method for controlling multi-bank embedded DRAM' [patent_app_type] => B2 [patent_app_number] => 09/942389 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3891 [patent_no_of_claims] => 102 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789155.pdf [firstpage_image] =>[orig_patent_app_number] => 09942389 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1155023 [patent_doc_number] => 06779075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'DDR and QDR converter and interface card, motherboard and memory module interface using the same' [patent_app_type] => B2 [patent_app_number] => 09/932627 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3536 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779075.pdf [firstpage_image] =>[orig_patent_app_number] => 09932627 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6143541 [patent_doc_number] => 20020002657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Cache system for concurrent processes' [patent_app_type] => new [patent_app_number] => 09/924289 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6090 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20020002657.pdf [firstpage_image] =>[orig_patent_app_number] => 09924289 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1106215 [patent_doc_number] => 06816947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'System and method for memory arbitration' [patent_app_type] => B1 [patent_app_number] => 09/909705 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816947.pdf [firstpage_image] =>[orig_patent_app_number] => 09909705 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6775515 [patent_doc_number] => 20030018853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Method and apparatus for filling lines in a cache' [patent_app_type] => new [patent_app_number] => 09/909562 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018853.pdf [firstpage_image] =>[orig_patent_app_number] => 09909562 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6836102 [patent_doc_number] => 20030163648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Coherence-free cache' [patent_app_type] => new [patent_app_number] => 10/312117 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163648.pdf [firstpage_image] =>[orig_patent_app_number] => 10312117 [rel_patent_id] =>[rel_patent_doc_number] =>)