Search

Nasser Moazzami Goodarzi

Examiner (ID: 5601)

Most Active Art Unit
2187
Art Unit(s)
2752, 2436, 2136, 2187, 2426, 2759
Total Applications
565
Issued Applications
483
Pending Applications
26
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1324048 [patent_doc_number] => 06611902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Information processor and information processing method' [patent_app_type] => B2 [patent_app_number] => 09/964604 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7208 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611902.pdf [firstpage_image] =>[orig_patent_app_number] => 09964604 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/964604
Information processor and information processing method Sep 27, 2001 Issued
Array ( [id] => 1184696 [patent_doc_number] => 06748488 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-08 [patent_title] => 'Storage array having multiple erasure correction and sub-stripe writing' [patent_app_type] => B2 [patent_app_number] => 09/966842 [patent_app_country] => US [patent_app_date] => 2001-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6867 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/748/06748488.pdf [firstpage_image] =>[orig_patent_app_number] => 09966842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/966842
Storage array having multiple erasure correction and sub-stripe writing Sep 27, 2001 Issued
Array ( [id] => 6348810 [patent_doc_number] => 20020035663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-21 [patent_title] => 'Method of validating data in circular buffers' [patent_app_type] => new [patent_app_number] => 09/950673 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2375 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0035/20020035663.pdf [firstpage_image] =>[orig_patent_app_number] => 09950673 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950673
Method of validating data in circular buffers Sep 12, 2001 Issued
Array ( [id] => 785866 [patent_doc_number] => 06993566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Entity self-clustering and host-entity communication such as via shared memory' [patent_app_type] => utility [patent_app_number] => 09/952592 [patent_app_country] => US [patent_app_date] => 2001-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5441 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993566.pdf [firstpage_image] =>[orig_patent_app_number] => 09952592 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/952592
Entity self-clustering and host-entity communication such as via shared memory Sep 12, 2001 Issued
Array ( [id] => 1353288 [patent_doc_number] => 06594739 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Memory system and method of using same' [patent_app_type] => B1 [patent_app_number] => 09/950546 [patent_app_country] => US [patent_app_date] => 2001-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13306 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594739.pdf [firstpage_image] =>[orig_patent_app_number] => 09950546 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/950546
Memory system and method of using same Sep 10, 2001 Issued
Array ( [id] => 7630004 [patent_doc_number] => 06636935 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-21 [patent_title] => 'Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules' [patent_app_type] => B1 [patent_app_number] => 09/948755 [patent_app_country] => US [patent_app_date] => 2001-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 18004 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/636/06636935.pdf [firstpage_image] =>[orig_patent_app_number] => 09948755 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/948755
Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules Sep 9, 2001 Issued
Array ( [id] => 1138905 [patent_doc_number] => 06789155 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'System and method for controlling multi-bank embedded DRAM' [patent_app_type] => B2 [patent_app_number] => 09/942389 [patent_app_country] => US [patent_app_date] => 2001-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3891 [patent_no_of_claims] => 102 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789155.pdf [firstpage_image] =>[orig_patent_app_number] => 09942389 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/942389
System and method for controlling multi-bank embedded DRAM Aug 28, 2001 Issued
Array ( [id] => 1155023 [patent_doc_number] => 06779075 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'DDR and QDR converter and interface card, motherboard and memory module interface using the same' [patent_app_type] => B2 [patent_app_number] => 09/932627 [patent_app_country] => US [patent_app_date] => 2001-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 3536 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/779/06779075.pdf [firstpage_image] =>[orig_patent_app_number] => 09932627 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/932627
DDR and QDR converter and interface card, motherboard and memory module interface using the same Aug 16, 2001 Issued
Array ( [id] => 6143541 [patent_doc_number] => 20020002657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-03 [patent_title] => 'Cache system for concurrent processes' [patent_app_type] => new [patent_app_number] => 09/924289 [patent_app_country] => US [patent_app_date] => 2001-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6090 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20020002657.pdf [firstpage_image] =>[orig_patent_app_number] => 09924289 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/924289
Cache system for concurrent processes Aug 7, 2001 Issued
Array ( [id] => 1106215 [patent_doc_number] => 06816947 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-09 [patent_title] => 'System and method for memory arbitration' [patent_app_type] => B1 [patent_app_number] => 09/909705 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 10 [patent_no_of_words] => 4714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/816/06816947.pdf [firstpage_image] =>[orig_patent_app_number] => 09909705 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909705
System and method for memory arbitration Jul 19, 2001 Issued
Array ( [id] => 6775515 [patent_doc_number] => 20030018853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-23 [patent_title] => 'Method and apparatus for filling lines in a cache' [patent_app_type] => new [patent_app_number] => 09/909562 [patent_app_country] => US [patent_app_date] => 2001-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20030018853.pdf [firstpage_image] =>[orig_patent_app_number] => 09909562 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/909562
Method and apparatus for filling lines in a cache Jul 19, 2001 Issued
Array ( [id] => 6836102 [patent_doc_number] => 20030163648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-28 [patent_title] => 'Coherence-free cache' [patent_app_type] => new [patent_app_number] => 10/312117 [patent_app_country] => US [patent_app_date] => 2003-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3213 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0163/20030163648.pdf [firstpage_image] =>[orig_patent_app_number] => 10312117 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/312117
Coherence-free cache Jun 21, 2001 Issued
Array ( [id] => 6332573 [patent_doc_number] => 20020198608 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-26 [patent_title] => 'System for addressing processors connected to a peripheral bus' [patent_app_type] => new [patent_app_number] => 09/886190 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3417 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0198/20020198608.pdf [firstpage_image] =>[orig_patent_app_number] => 09886190 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886190
System for addressing processors connected to a peripheral bus Jun 20, 2001 Issued
Array ( [id] => 6245279 [patent_doc_number] => 20020046297 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'System containing a plurality of central processing units' [patent_app_type] => new [patent_app_number] => 09/886558 [patent_app_country] => US [patent_app_date] => 2001-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5314 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046297.pdf [firstpage_image] =>[orig_patent_app_number] => 09886558 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/886558
System containing a plurality of central processing units Jun 20, 2001 Abandoned
Array ( [id] => 1431871 [patent_doc_number] => 06516383 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Techniques for efficient location of free entries for TCAM inserts' [patent_app_type] => B1 [patent_app_number] => 09/871321 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5027 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/516/06516383.pdf [firstpage_image] =>[orig_patent_app_number] => 09871321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871321
Techniques for efficient location of free entries for TCAM inserts May 29, 2001 Issued
Array ( [id] => 1225645 [patent_doc_number] => 06704848 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-09 [patent_title] => 'Apparatus for controlling time deinterleaver memory for digital audio broadcasting' [patent_app_type] => B2 [patent_app_number] => 09/866864 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4610 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704848.pdf [firstpage_image] =>[orig_patent_app_number] => 09866864 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866864
Apparatus for controlling time deinterleaver memory for digital audio broadcasting May 29, 2001 Issued
Array ( [id] => 1308950 [patent_doc_number] => 06629230 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-30 [patent_title] => 'Host interface circuit' [patent_app_type] => B2 [patent_app_number] => 09/871144 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 8648 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629230.pdf [firstpage_image] =>[orig_patent_app_number] => 09871144 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/871144
Host interface circuit May 29, 2001 Issued
Array ( [id] => 6424843 [patent_doc_number] => 20020184451 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Unifying data storage in a distributed network' [patent_app_type] => new [patent_app_number] => 09/866735 [patent_app_country] => US [patent_app_date] => 2001-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4631 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184451.pdf [firstpage_image] =>[orig_patent_app_number] => 09866735 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/866735
Unifying data storage in a distributed network May 29, 2001 Issued
Array ( [id] => 6245409 [patent_doc_number] => 20020046332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'Multi task information recordation system and information storage medium' [patent_app_type] => new [patent_app_number] => 09/865676 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5602 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20020046332.pdf [firstpage_image] =>[orig_patent_app_number] => 09865676 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/865676
Multi task information recordation system and information storage medium May 28, 2001 Issued
Array ( [id] => 6424817 [patent_doc_number] => 20020184448 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Method for cache replacement of web documents' [patent_app_type] => new [patent_app_number] => 09/870060 [patent_app_country] => US [patent_app_date] => 2001-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4222 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0184/20020184448.pdf [firstpage_image] =>[orig_patent_app_number] => 09870060 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870060
Method for cache replacement of web documents May 28, 2001 Issued
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