
Nasser Moazzami Goodarzi
Supervisory Patent Examiner (ID: 12173, Phone: (571)272-4195 , Office: P/2426 )
| Most Active Art Unit | 2187 |
| Art Unit(s) | 2187, 2436, 2752, 2136, 2759, 2426 |
| Total Applications | 556 |
| Issued Applications | 479 |
| Pending Applications | 21 |
| Abandoned Applications | 58 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 4254956
[patent_doc_number] => 06119199
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-12
[patent_title] => 'Information processing system'
[patent_app_type] => 1
[patent_app_number] => 8/934064
[patent_app_country] => US
[patent_app_date] => 1997-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 13
[patent_no_of_words] => 8068
[patent_no_of_claims] => 31
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/119/06119199.pdf
[firstpage_image] =>[orig_patent_app_number] => 934064
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/934064 | Information processing system | Sep 18, 1997 | Issued |
Array
(
[id] => 4239049
[patent_doc_number] => 06088774
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-07-11
[patent_title] => 'Read/write timing for maximum utilization of bidirectional read/write bus'
[patent_app_type] => 1
[patent_app_number] => 8/933673
[patent_app_country] => US
[patent_app_date] => 1997-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 8
[patent_no_of_words] => 4620
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/088/06088774.pdf
[firstpage_image] =>[orig_patent_app_number] => 933673
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/933673 | Read/write timing for maximum utilization of bidirectional read/write bus | Sep 18, 1997 | Issued |
Array
(
[id] => 4199036
[patent_doc_number] => 06038639
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-14
[patent_title] => 'Data file storage management system for snapshot copy operations'
[patent_app_type] => 1
[patent_app_number] => 8/925787
[patent_app_country] => US
[patent_app_date] => 1997-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 20
[patent_no_of_words] => 13973
[patent_no_of_claims] => 28
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 185
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/038/06038639.pdf
[firstpage_image] =>[orig_patent_app_number] => 925787
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/925787 | Data file storage management system for snapshot copy operations | Sep 8, 1997 | Issued |
Array
(
[id] => 4422377
[patent_doc_number] => 06173362
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-01-09
[patent_title] => 'Storage system with selective optimization of data location'
[patent_app_type] => 1
[patent_app_number] => 8/917351
[patent_app_country] => US
[patent_app_date] => 1997-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 14
[patent_no_of_words] => 6031
[patent_no_of_claims] => 66
[patent_no_of_ind_claims] => 16
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/173/06173362.pdf
[firstpage_image] =>[orig_patent_app_number] => 917351
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/917351 | Storage system with selective optimization of data location | Aug 25, 1997 | Issued |
Array
(
[id] => 4179036
[patent_doc_number] => 06115783
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-09-05
[patent_title] => 'Integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 8/911935
[patent_app_country] => US
[patent_app_date] => 1997-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 2142
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 316
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/115/06115783.pdf
[firstpage_image] =>[orig_patent_app_number] => 911935
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/911935 | Integrated circuit | Aug 14, 1997 | Issued |
Array
(
[id] => 4211265
[patent_doc_number] => 06044435
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-28
[patent_title] => 'Method for determining allocatability of tape drives to serve requests to store information'
[patent_app_type] => 1
[patent_app_number] => 8/900460
[patent_app_country] => US
[patent_app_date] => 1997-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 8753
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/044/06044435.pdf
[firstpage_image] =>[orig_patent_app_number] => 900460
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/900460 | Method for determining allocatability of tape drives to serve requests to store information | Jul 24, 1997 | Issued |
Array
(
[id] => 4270171
[patent_doc_number] => 06223256
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-24
[patent_title] => 'Computer cache memory with classes and dynamic selection of replacement algorithms'
[patent_app_type] => 1
[patent_app_number] => 8/898637
[patent_app_country] => US
[patent_app_date] => 1997-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 7421
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/223/06223256.pdf
[firstpage_image] =>[orig_patent_app_number] => 898637
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/898637 | Computer cache memory with classes and dynamic selection of replacement algorithms | Jul 21, 1997 | Issued |
Array
(
[id] => 4192584
[patent_doc_number] => 06141736
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-10-31
[patent_title] => 'Arrangement with master and slave units'
[patent_app_type] => 1
[patent_app_number] => 8/836590
[patent_app_country] => US
[patent_app_date] => 1997-07-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4048
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/141/06141736.pdf
[firstpage_image] =>[orig_patent_app_number] => 836590
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/836590 | Arrangement with master and slave units | Jul 20, 1997 | Issued |
Array
(
[id] => 3947296
[patent_doc_number] => 05953738
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-14
[patent_title] => 'DRAM with integral SRAM and arithmetic-logic units'
[patent_app_type] => 1
[patent_app_number] => 8/886952
[patent_app_country] => US
[patent_app_date] => 1997-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 17
[patent_no_of_words] => 8533
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/953/05953738.pdf
[firstpage_image] =>[orig_patent_app_number] => 886952
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/886952 | DRAM with integral SRAM and arithmetic-logic units | Jul 1, 1997 | Issued |
Array
(
[id] => 4310241
[patent_doc_number] => 06212609
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-04-03
[patent_title] => 'Alternate access mechanism for saving and restoring state of read-only register'
[patent_app_type] => 1
[patent_app_number] => 8/884785
[patent_app_country] => US
[patent_app_date] => 1997-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 3716
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/212/06212609.pdf
[firstpage_image] =>[orig_patent_app_number] => 884785
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/884785 | Alternate access mechanism for saving and restoring state of read-only register | Jun 29, 1997 | Issued |
Array
(
[id] => 4011059
[patent_doc_number] => 05920889
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer'
[patent_app_type] => 1
[patent_app_number] => 8/883863
[patent_app_country] => US
[patent_app_date] => 1997-06-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4156
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920889.pdf
[firstpage_image] =>[orig_patent_app_number] => 883863
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/883863 | Apparatus and method for write miss processing in a copy-back data cache with an allocating load buffer and a non-allocating store buffer | Jun 26, 1997 | Issued |
Array
(
[id] => 3960266
[patent_doc_number] => 05930819
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache'
[patent_app_type] => 1
[patent_app_number] => 8/881238
[patent_app_country] => US
[patent_app_date] => 1997-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8777
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930819.pdf
[firstpage_image] =>[orig_patent_app_number] => 881238
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881238 | Method for performing in-line bank conflict detection and resolution in a multi-ported non-blocking cache | Jun 24, 1997 | Issued |
Array
(
[id] => 4138940
[patent_doc_number] => 06073225
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-06-06
[patent_title] => 'Method and apparatus for monitoring bus transactions based on cycle type and memory address range'
[patent_app_type] => 1
[patent_app_number] => 8/881414
[patent_app_country] => US
[patent_app_date] => 1997-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 3777
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/073/06073225.pdf
[firstpage_image] =>[orig_patent_app_number] => 881414
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881414 | Method and apparatus for monitoring bus transactions based on cycle type and memory address range | Jun 23, 1997 | Issued |
Array
(
[id] => 4092371
[patent_doc_number] => 05966733
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-10-12
[patent_title] => 'Optimizing data movement with hardware operations'
[patent_app_type] => 1
[patent_app_number] => 8/881346
[patent_app_country] => US
[patent_app_date] => 1997-06-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 17
[patent_no_of_words] => 11509
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/966/05966733.pdf
[firstpage_image] =>[orig_patent_app_number] => 881346
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/881346 | Optimizing data movement with hardware operations | Jun 23, 1997 | Issued |
| 08/793479 | CACHE SYSTEM FOR STORING DATA | Jun 17, 1997 | Abandoned |
Array
(
[id] => 4103689
[patent_doc_number] => 06026466
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-15
[patent_title] => 'Multiple row address strobe DRAM architecture to improve bandwidth'
[patent_app_type] => 1
[patent_app_number] => 8/876997
[patent_app_country] => US
[patent_app_date] => 1997-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 7919
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/026/06026466.pdf
[firstpage_image] =>[orig_patent_app_number] => 876997
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/876997 | Multiple row address strobe DRAM architecture to improve bandwidth | Jun 15, 1997 | Issued |
Array
(
[id] => 3970419
[patent_doc_number] => 05991847
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Data pattern caching for speeding up write operations'
[patent_app_type] => 1
[patent_app_number] => 8/870980
[patent_app_country] => US
[patent_app_date] => 1997-06-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 8
[patent_no_of_words] => 5338
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 95
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/991/05991847.pdf
[firstpage_image] =>[orig_patent_app_number] => 870980
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/870980 | Data pattern caching for speeding up write operations | Jun 5, 1997 | Issued |
Array
(
[id] => 4011128
[patent_doc_number] => 05920893
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-06
[patent_title] => 'Storage control and computer system using the same'
[patent_app_type] => 1
[patent_app_number] => 8/867191
[patent_app_country] => US
[patent_app_date] => 1997-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 4313
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 143
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/920/05920893.pdf
[firstpage_image] =>[orig_patent_app_number] => 867191
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/867191 | Storage control and computer system using the same | Jun 1, 1997 | Issued |
Array
(
[id] => 4176647
[patent_doc_number] => 06157984
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-12-05
[patent_title] => 'Integrated controller/processor for disc drive having direct memory access'
[patent_app_type] => 1
[patent_app_number] => 8/856648
[patent_app_country] => US
[patent_app_date] => 1997-05-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 35
[patent_figures_cnt] => 36
[patent_no_of_words] => 8570
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/157/06157984.pdf
[firstpage_image] =>[orig_patent_app_number] => 856648
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/856648 | Integrated controller/processor for disc drive having direct memory access | May 14, 1997 | Issued |
Array
(
[id] => 3960300
[patent_doc_number] => 05930821
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-07-27
[patent_title] => 'Method and apparatus for shared cache lines in split data/code caches'
[patent_app_type] => 1
[patent_app_number] => 8/854641
[patent_app_country] => US
[patent_app_date] => 1997-05-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 7053
[patent_no_of_claims] => 45
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 98
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/930/05930821.pdf
[firstpage_image] =>[orig_patent_app_number] => 854641
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/854641 | Method and apparatus for shared cache lines in split data/code caches | May 11, 1997 | Issued |