
Natalia A. Gondarenko
Examiner (ID: 11539, Phone: (571)272-2284 , Office: P/2891 )
| Most Active Art Unit | 2891 |
| Art Unit(s) | 2891 |
| Total Applications | 933 |
| Issued Applications | 588 |
| Pending Applications | 124 |
| Abandoned Applications | 249 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19176265
[patent_doc_number] => 20240162239
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-05-16
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/381525
[patent_app_country] => US
[patent_app_date] => 2023-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13730
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -28
[patent_words_short_claim] => 116
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18381525
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/381525 | DISPLAY PANEL AND DISPLAY DEVICE | Oct 17, 2023 | Pending |
Array
(
[id] => 18961211
[patent_doc_number] => 20240049538
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-08
[patent_title] => DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/488449
[patent_app_country] => US
[patent_app_date] => 2023-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8735
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 257
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18488449
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/488449 | DISPLAY PANEL AND DISPLAY DEVICE | Oct 16, 2023 | Pending |
Array
(
[id] => 19392922
[patent_doc_number] => 20240282792
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-08-22
[patent_title] => IMAGE SENSOR
[patent_app_type] => utility
[patent_app_number] => 18/379426
[patent_app_country] => US
[patent_app_date] => 2023-10-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14095
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379426
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/379426 | IMAGE SENSOR | Oct 11, 2023 | Pending |
Array
(
[id] => 19986998
[patent_doc_number] => 20250125220
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-04-17
[patent_title] => INVERTED MEMORY STACK
[patent_app_type] => utility
[patent_app_number] => 18/379133
[patent_app_country] => US
[patent_app_date] => 2023-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 0
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -23
[patent_words_short_claim] => 47
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379133
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/379133 | INVERTED MEMORY STACK | Oct 10, 2023 | Pending |
Array
(
[id] => 18927347
[patent_doc_number] => 20240030351
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => Field-Effect Transistor, Production Method Thereof, Switching Circuit, and Circuit Board
[patent_app_type] => utility
[patent_app_number] => 18/477831
[patent_app_country] => US
[patent_app_date] => 2023-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6770
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 74
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477831
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/477831 | Field-Effect Transistor, Production Method Thereof, Switching Circuit, and Circuit Board | Sep 28, 2023 | Pending |
Array
(
[id] => 18882949
[patent_doc_number] => 20240006318
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-04
[patent_title] => POWER RAIL AND SIGNAL LINE ARRANGEMENT IN INTEGRATED CIRCUITS HAVING STACKED TRANSISTORS
[patent_app_type] => utility
[patent_app_number] => 18/469309
[patent_app_country] => US
[patent_app_date] => 2023-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 19641
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 229
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18469309
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/469309 | Power rail and signal line arrangement in integrated circuits having stacked transistors | Sep 17, 2023 | Issued |
Array
(
[id] => 18866060
[patent_doc_number] => 20230420497
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-28
[patent_title] => POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE
[patent_app_type] => utility
[patent_app_number] => 18/464938
[patent_app_country] => US
[patent_app_date] => 2023-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15082
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 236
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18464938
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/464938 | POWER DEVICE INTEGRATION ON A COMMON SUBSTRATE | Sep 10, 2023 | Pending |
Array
(
[id] => 19452955
[patent_doc_number] => 20240313085
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-09-19
[patent_title] => HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/463253
[patent_app_country] => US
[patent_app_date] => 2023-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5003
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18463253
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/463253 | HIGH ELECTRON MOBILITY TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME | Sep 6, 2023 | Pending |
Array
(
[id] => 20216219
[patent_doc_number] => 12412874
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-09-09
[patent_title] => Pixel array package structure and display panel
[patent_app_type] => utility
[patent_app_number] => 18/460673
[patent_app_country] => US
[patent_app_date] => 2023-09-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 21
[patent_no_of_words] => 0
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18460673
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/460673 | Pixel array package structure and display panel | Sep 3, 2023 | Issued |
Array
(
[id] => 19823292
[patent_doc_number] => 20250081499
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 18/459079
[patent_app_country] => US
[patent_app_date] => 2023-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7960
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 50
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459079
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459079 | SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME | Aug 30, 2023 | Pending |
Array
(
[id] => 19255176
[patent_doc_number] => 20240206173
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-06-20
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/459339
[patent_app_country] => US
[patent_app_date] => 2023-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6547
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 189
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18459339
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/459339 | SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE | Aug 30, 2023 | Pending |
Array
(
[id] => 19823340
[patent_doc_number] => 20250081547
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => High Voltage Breakdown Resistant Bipolar Transistor
[patent_app_type] => utility
[patent_app_number] => 18/240721
[patent_app_country] => US
[patent_app_date] => 2023-08-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 2778
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18240721
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/240721 | High Voltage Breakdown Resistant Bipolar Transistor | Aug 30, 2023 | Pending |
Array
(
[id] => 19057031
[patent_doc_number] => 20240099000
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/458284
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12031
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458284
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458284 | SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE | Aug 29, 2023 | Pending |
Array
(
[id] => 19823287
[patent_doc_number] => 20250081494
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2025-03-06
[patent_title] => RECESSED GATE HEMT PROCESSING WITH REVERSED ETCHING
[patent_app_type] => utility
[patent_app_number] => 18/458877
[patent_app_country] => US
[patent_app_date] => 2023-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5760
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458877
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/458877 | RECESSED GATE HEMT PROCESSING WITH REVERSED ETCHING | Aug 29, 2023 | Pending |
Array
(
[id] => 18835340
[patent_doc_number] => 20230403867
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-12-14
[patent_title] => Memory Arrays Comprising Vertically-Alternating Tiers of Insulative Material and Memory Cells and Methods of Forming a Memory Array
[patent_app_type] => utility
[patent_app_number] => 18/239063
[patent_app_country] => US
[patent_app_date] => 2023-08-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5525
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -14
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18239063
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/239063 | Memory arrays comprising vertically-alternating tiers of insulative material and memory cells and methods of forming a memory array | Aug 27, 2023 | Issued |
Array
(
[id] => 19057131
[patent_doc_number] => 20240099100
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-03-21
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/451682
[patent_app_country] => US
[patent_app_date] => 2023-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11146
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 5
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451682
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/451682 | DISPLAY DEVICE | Aug 16, 2023 | Pending |
Array
(
[id] => 18789499
[patent_doc_number] => 20230378172
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => SEMICONDUCTOR DEVICE WITH CONTROLLABLE CHANNEL LENGTH AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 18/366350
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7443
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -10
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18366350
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/366350 | Semiconductor device with controllable channel length and manufacturing method thereof | Aug 6, 2023 | Issued |
Array
(
[id] => 19951282
[patent_doc_number] => 12322653
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-06-03
[patent_title] => Self-aligned metal gate for multigate device and method of forming thereof
[patent_app_type] => utility
[patent_app_number] => 18/231076
[patent_app_country] => US
[patent_app_date] => 2023-08-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 32
[patent_figures_cnt] => 44
[patent_no_of_words] => 6642
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 215
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18231076
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/231076 | Self-aligned metal gate for multigate device and method of forming thereof | Aug 6, 2023 | Issued |
Array
(
[id] => 19887008
[patent_doc_number] => 12272741
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-08
[patent_title] => Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance
[patent_app_type] => utility
[patent_app_number] => 18/364679
[patent_app_country] => US
[patent_app_date] => 2023-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 13
[patent_no_of_words] => 8304
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364679
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/364679 | Integration of p-channel and n-channel E-FET III-V devices with optimization of device performance | Aug 2, 2023 | Issued |
Array
(
[id] => 18991247
[patent_doc_number] => 20240063216
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-02-22
[patent_title] => SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE
[patent_app_type] => utility
[patent_app_number] => 18/364494
[patent_app_country] => US
[patent_app_date] => 2023-08-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4362
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18364494
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/364494 | SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE | Aug 2, 2023 | Pending |