Natalia Harkaway
Examiner (ID: 8787)
Most Active Art Unit | 1201 |
Art Unit(s) | 1201 |
Total Applications | 161 |
Issued Applications | 154 |
Pending Applications | 0 |
Abandoned Applications | 7 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17752892
[patent_doc_number] => 20220231097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-07-21
[patent_title] => DISPLAY SCREEN, METHOD FOR MANUFACTURING SAME AND DISPLAY TERMINAL
[patent_app_type] => utility
[patent_app_number] => 17/546932
[patent_app_country] => US
[patent_app_date] => 2021-12-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6378
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17546932
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/546932 | DISPLAY SCREEN, METHOD FOR MANUFACTURING SAME AND DISPLAY TERMINAL | Dec 8, 2021 | Pending |
Array
(
[id] => 18409032
[patent_doc_number] => 20230170385
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-06-01
[patent_title] => ESD PROTECTION DEVICE WITH ISOLATION STRUCTURE LAYOUT THAT MINIMIZES HARMONIC DISTORTION
[patent_app_type] => utility
[patent_app_number] => 17/536253
[patent_app_country] => US
[patent_app_date] => 2021-11-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6416
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17536253
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/536253 | ESD protection device with isolation structure layout that minimizes harmonic distortion | Nov 28, 2021 | Issued |
Array
(
[id] => 19370543
[patent_doc_number] => 12062637
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-13
[patent_title] => Electronic device
[patent_app_type] => utility
[patent_app_number] => 17/534414
[patent_app_country] => US
[patent_app_date] => 2021-11-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 16
[patent_no_of_words] => 7456
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 203
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17534414
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/534414 | Electronic device | Nov 22, 2021 | Issued |
Array
(
[id] => 18271686
[patent_doc_number] => 20230092928
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-23
[patent_title] => SEMICONDUCTOR MEMORY DEVICE AND FABRICATION METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/528152
[patent_app_country] => US
[patent_app_date] => 2021-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6884
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17528152
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/528152 | Semiconductor memory device | Nov 15, 2021 | Issued |
Array
(
[id] => 17448149
[patent_doc_number] => 20220068654
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => SEMICONDUCTOR MEMORY STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 17/523439
[patent_app_country] => US
[patent_app_date] => 2021-11-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5768
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 79
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523439
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/523439 | Semiconductor memory structure | Nov 9, 2021 | Issued |
Array
(
[id] => 17431833
[patent_doc_number] => 20220059542
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/520519
[patent_app_country] => US
[patent_app_date] => 2021-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10090
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => 0
[patent_words_short_claim] => 20
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520519
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520519 | Method for fabricating semiconductor device | Nov 4, 2021 | Issued |
Array
(
[id] => 18248961
[patent_doc_number] => 11605557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-14
[patent_title] => Method for preparing semiconductor device with metal plug having rounded top surface
[patent_app_type] => utility
[patent_app_number] => 17/520536
[patent_app_country] => US
[patent_app_date] => 2021-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 8651
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 142
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520536
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520536 | Method for preparing semiconductor device with metal plug having rounded top surface | Nov 4, 2021 | Issued |
Array
(
[id] => 18494196
[patent_doc_number] => 11699617
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Method for fabricating semiconductor device with alleviation feature
[patent_app_type] => utility
[patent_app_number] => 17/520560
[patent_app_country] => US
[patent_app_date] => 2021-11-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 40
[patent_figures_cnt] => 40
[patent_no_of_words] => 9247
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520560
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/520560 | Method for fabricating semiconductor device with alleviation feature | Nov 4, 2021 | Issued |
Array
(
[id] => 18919221
[patent_doc_number] => 11881512
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-01-23
[patent_title] => Method of manufacturing semiconductor device with silicon carbide body
[patent_app_type] => utility
[patent_app_number] => 17/519161
[patent_app_country] => US
[patent_app_date] => 2021-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 47
[patent_no_of_words] => 12514
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 245
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17519161
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/519161 | Method of manufacturing semiconductor device with silicon carbide body | Nov 3, 2021 | Issued |
Array
(
[id] => 18334630
[patent_doc_number] => 20230126578
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-04-27
[patent_title] => VERTICAL BIPOLAR JUNCTION TRANSISTOR AND VERTICAL FIELD EFFECT TRANSISTOR WITH SHARED FLOATING REGION
[patent_app_type] => utility
[patent_app_number] => 17/506913
[patent_app_country] => US
[patent_app_date] => 2021-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10345
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 109
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506913
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/506913 | Vertical bipolar junction transistor and vertical field effect transistor with shared floating region | Oct 20, 2021 | Issued |
Array
(
[id] => 17949557
[patent_doc_number] => 20220336576
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-20
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/488277
[patent_app_country] => US
[patent_app_date] => 2021-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8634
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488277
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/488277 | SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF | Sep 27, 2021 | Pending |
Array
(
[id] => 18448335
[patent_doc_number] => 11683927
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-06-20
[patent_title] => Integrated circuitry, DRAM circuitry
[patent_app_type] => utility
[patent_app_number] => 17/473145
[patent_app_country] => US
[patent_app_date] => 2021-09-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 34
[patent_no_of_words] => 5700
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473145
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/473145 | Integrated circuitry, DRAM circuitry | Sep 12, 2021 | Issued |
Array
(
[id] => 17278253
[patent_doc_number] => 20210384451
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-09
[patent_title] => DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/409886
[patent_app_country] => US
[patent_app_date] => 2021-08-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8798
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -4
[patent_words_short_claim] => 208
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17409886
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/409886 | Display device | Aug 23, 2021 | Issued |
Array
(
[id] => 18210082
[patent_doc_number] => 20230056343
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-23
[patent_title] => APPARATUSES INCLUDING CONTACTS IN A PERIPHERAL REGION AND METHODS FOR FORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/407030
[patent_app_country] => US
[patent_app_date] => 2021-08-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4866
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17407030
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/407030 | Apparatuses including contacts in a peripheral region | Aug 18, 2021 | Issued |
Array
(
[id] => 19376795
[patent_doc_number] => 12068376
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-20
[patent_title] => Metal field plates
[patent_app_type] => utility
[patent_app_number] => 17/394476
[patent_app_country] => US
[patent_app_date] => 2021-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 15
[patent_no_of_words] => 6657
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 194
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17394476
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/394476 | Metal field plates | Aug 4, 2021 | Issued |
Array
(
[id] => 17745729
[patent_doc_number] => 11393811
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Bipolar junction transistor having an integrated switchable short
[patent_app_type] => utility
[patent_app_number] => 17/391114
[patent_app_country] => US
[patent_app_date] => 2021-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 3392
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 26
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391114
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/391114 | Bipolar junction transistor having an integrated switchable short | Aug 1, 2021 | Issued |
Array
(
[id] => 18164248
[patent_doc_number] => 20230030843
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-02-02
[patent_title] => SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/390492
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5027
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17390492
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/390492 | SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME | Jul 29, 2021 | Abandoned |
Array
(
[id] => 18078921
[patent_doc_number] => 20220404533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-22
[patent_title] => QUANTUM DOT COLOR FILTER SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/440795
[patent_app_country] => US
[patent_app_date] => 2021-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9609
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17440795
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/440795 | QUANTUM DOT COLOR FILTER SUBSTRATE, METHOD FOR MANUFACTURING SAME, AND DISPLAY DEVICE | Jul 29, 2021 | Pending |
Array
(
[id] => 17232185
[patent_doc_number] => 20210358742
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-11-18
[patent_title] => DISPLAY WITH COLOR CONVERSION LAYER AND ISOLATION WALLS
[patent_app_type] => utility
[patent_app_number] => 17/389029
[patent_app_country] => US
[patent_app_date] => 2021-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4686
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 18
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17389029
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/389029 | Display with color conversion layer and isolation walls | Jul 28, 2021 | Issued |
Array
(
[id] => 19277237
[patent_doc_number] => 12027369
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-02
[patent_title] => Mask structure, semiconductor structure and methods for manufacturing same
[patent_app_type] => utility
[patent_app_number] => 17/604057
[patent_app_country] => US
[patent_app_date] => 2021-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 4562
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 222
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17604057
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/604057 | Mask structure, semiconductor structure and methods for manufacturing same | Jul 13, 2021 | Issued |