Search

Natalie K. Walford

Examiner (ID: 11334)

Most Active Art Unit
2879
Art Unit(s)
2879
Total Applications
668
Issued Applications
464
Pending Applications
1
Abandoned Applications
210

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17431763 [patent_doc_number] => 20220059472 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-24 [patent_title] => SEMICONDUCTOR SUBSTRATE AND METHOD OF SAWING THE SAME [patent_app_type] => utility [patent_app_number] => 17/216279 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4746 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17216279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/216279
Semiconductor substrate and method of sawing the same Mar 28, 2021 Issued
Array ( [id] => 17855174 [patent_doc_number] => 20220285217 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => WAFER THINNING METHOD [patent_app_type] => utility [patent_app_number] => 17/215417 [patent_app_country] => US [patent_app_date] => 2021-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17215417 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/215417
WAFER THINNING METHOD Mar 28, 2021 Abandoned
Array ( [id] => 18796989 [patent_doc_number] => 11830824 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-28 [patent_title] => Edge protection on semiconductor substrates [patent_app_type] => utility [patent_app_number] => 17/214411 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 7640 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17214411 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/214411
Edge protection on semiconductor substrates Mar 25, 2021 Issued
Array ( [id] => 17901115 [patent_doc_number] => 20220310777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => INTEGRATED CIRCUIT PACKAGE REDISTRIBUTION LAYERS WITH METAL-INSULATOR-METAL (MIM) CAPACITORS [patent_app_type] => utility [patent_app_number] => 17/213551 [patent_app_country] => US [patent_app_date] => 2021-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9708 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17213551 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/213551
Integrated circuit package redistribution layers with metal-insulator-metal (MIM) capacitors Mar 25, 2021 Issued
Array ( [id] => 17730732 [patent_doc_number] => 11387133 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-12 [patent_title] => Wafer processing method [patent_app_type] => utility [patent_app_number] => 17/211186 [patent_app_country] => US [patent_app_date] => 2021-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4763 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17211186 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/211186
Wafer processing method Mar 23, 2021 Issued
Array ( [id] => 17772337 [patent_doc_number] => 11404288 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2022-08-02 [patent_title] => Semiconductor device packaging warpage control [patent_app_type] => utility [patent_app_number] => 17/209710 [patent_app_country] => US [patent_app_date] => 2021-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 5074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17209710 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/209710
Semiconductor device packaging warpage control Mar 22, 2021 Issued
Array ( [id] => 17196878 [patent_doc_number] => 11165655 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-11-02 [patent_title] => System for optimizing enterprise network relations [patent_app_type] => utility [patent_app_number] => 17/208758 [patent_app_country] => US [patent_app_date] => 2021-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 9884 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17208758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/208758
System for optimizing enterprise network relations Mar 21, 2021 Issued
Array ( [id] => 17886564 [patent_doc_number] => 20220302042 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => PLATED PILLAR DIES HAVING INTEGRATED ELECTROMAGNETIC SHIELD LAYERS [patent_app_type] => utility [patent_app_number] => 17/207022 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9991 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207022 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207022
Plated pillar dies having integrated electromagnetic shield layers Mar 18, 2021 Issued
Array ( [id] => 18263108 [patent_doc_number] => 11610817 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-21 [patent_title] => Method of processing a semiconductor wafer, semiconductor wafer, and semiconductor die produced from a semiconductor wafer [patent_app_type] => utility [patent_app_number] => 17/206782 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6256 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17206782 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/206782
Method of processing a semiconductor wafer, semiconductor wafer, and semiconductor die produced from a semiconductor wafer Mar 18, 2021 Issued
Array ( [id] => 18219500 [patent_doc_number] => 11594449 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Method of making a semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/207152 [patent_app_country] => US [patent_app_date] => 2021-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6297 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17207152 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/207152
Method of making a semiconductor structure Mar 18, 2021 Issued
Array ( [id] => 17886544 [patent_doc_number] => 20220302022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => SEMICONDUCTOR SUBSTRATE STRUCTURE AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/204829 [patent_app_country] => US [patent_app_date] => 2021-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17204829 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/204829
Semiconductor substrate structure and method of manufacturing the same Mar 16, 2021 Issued
Array ( [id] => 18593408 [patent_doc_number] => 11742320 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Wafer bonding alignment [patent_app_type] => utility [patent_app_number] => 17/249758 [patent_app_country] => US [patent_app_date] => 2021-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 23967 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17249758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/249758
Wafer bonding alignment Mar 10, 2021 Issued
Array ( [id] => 16981821 [patent_doc_number] => 20210226058 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-22 [patent_title] => NANOWIRE SEMICONDUCTOR DEVICE HAVING HIGH-QUALITY EPITAXIAL LAYER AND METHOD OF MANUFACTURING THE SAME [patent_app_type] => utility [patent_app_number] => 17/197930 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8535 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197930 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197930
Nanowire semiconductor device having high-quality epitaxial layer and method of manufacturing the same Mar 9, 2021 Issued
Array ( [id] => 19046706 [patent_doc_number] => 11935826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-19 [patent_title] => Capacitor between two passivation layers with different etching rates [patent_app_type] => utility [patent_app_number] => 17/197483 [patent_app_country] => US [patent_app_date] => 2021-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6242 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17197483 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/197483
Capacitor between two passivation layers with different etching rates Mar 9, 2021 Issued
Array ( [id] => 17917709 [patent_doc_number] => 20220320105 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SEMICONDUCTOR STRUCTURES AND MANUFACTURING METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 17/310645 [patent_app_country] => US [patent_app_date] => 2021-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4323 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17310645 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/310645
Semiconductor structures and manufacturing methods thereof Mar 7, 2021 Issued
Array ( [id] => 18840164 [patent_doc_number] => 11848243 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-19 [patent_title] => Molded semiconductor package having a substrate with bevelled edge [patent_app_type] => utility [patent_app_number] => 17/193737 [patent_app_country] => US [patent_app_date] => 2021-03-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 15 [patent_no_of_words] => 5768 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17193737 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/193737
Molded semiconductor package having a substrate with bevelled edge Mar 4, 2021 Issued
Array ( [id] => 17653653 [patent_doc_number] => 11356404 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-06-07 [patent_title] => Domain name system (DNS) override for edge computing [patent_app_type] => utility [patent_app_number] => 17/189796 [patent_app_country] => US [patent_app_date] => 2021-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11292 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17189796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/189796
Domain name system (DNS) override for edge computing Mar 1, 2021 Issued
Array ( [id] => 18857284 [patent_doc_number] => 11854879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Cu [patent_app_type] => utility [patent_app_number] => 17/184756 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 10827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17184756 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/184756
Cu Feb 24, 2021 Issued
Array ( [id] => 17146386 [patent_doc_number] => 20210314399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => METHOD AND APPARATUS FOR RECOVERING MISSING DATA IN MULTI-SOURCE HYBRID OVERLAY NETWORK [patent_app_type] => utility [patent_app_number] => 17/185413 [patent_app_country] => US [patent_app_date] => 2021-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8275 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17185413 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/185413
Method and apparatus for recovering missing data in multi-source hybrid overlay network Feb 24, 2021 Issued
Array ( [id] => 18382085 [patent_doc_number] => 20230157176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-05-18 [patent_title] => DISPLAYING SUBSTRATE, MANUFACTURING METHOD THEREOF, AND DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 17/432433 [patent_app_country] => US [patent_app_date] => 2021-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6327 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17432433 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/432433
Displaying substrate, manufacturing method thereof, and display panel Feb 22, 2021 Issued
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