
Natalie K. Walford
Examiner (ID: 11334)
| Most Active Art Unit | 2879 |
| Art Unit(s) | 2879 |
| Total Applications | 668 |
| Issued Applications | 464 |
| Pending Applications | 1 |
| Abandoned Applications | 210 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17347115
[patent_doc_number] => 20220013446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-13
[patent_title] => High Temperature Barrier Film For Molten Wafer Infusion
[patent_app_type] => utility
[patent_app_number] => 16/922220
[patent_app_country] => US
[patent_app_date] => 2020-07-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 3309
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16922220
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/922220 | High Temperature Barrier Film For Molten Wafer Infusion | Jul 6, 2020 | Abandoned |
Array
(
[id] => 17271207
[patent_doc_number] => 11196646
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-07
[patent_title] => Unique user session tracking in adaptive bitrate video delivery
[patent_app_type] => utility
[patent_app_number] => 16/920277
[patent_app_country] => US
[patent_app_date] => 2020-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3319
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 93
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16920277
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/920277 | Unique user session tracking in adaptive bitrate video delivery | Jul 1, 2020 | Issued |
Array
(
[id] => 18493942
[patent_doc_number] => 11699363
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Stretchable display device
[patent_app_type] => utility
[patent_app_number] => 16/913457
[patent_app_country] => US
[patent_app_date] => 2020-06-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 26
[patent_no_of_words] => 22608
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16913457
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/913457 | Stretchable display device | Jun 25, 2020 | Issued |
Array
(
[id] => 18494231
[patent_doc_number] => 11699652
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-11
[patent_title] => Microelectronic devices and electronic systems
[patent_app_type] => utility
[patent_app_number] => 16/905698
[patent_app_country] => US
[patent_app_date] => 2020-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 14231
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 176
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16905698
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/905698 | Microelectronic devices and electronic systems | Jun 17, 2020 | Issued |
Array
(
[id] => 17986011
[patent_doc_number] => 20220352048
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-11-03
[patent_title] => Method of Manufacturing Semiconductor Chips having a Side Wall Sealing
[patent_app_type] => utility
[patent_app_number] => 17/620342
[patent_app_country] => US
[patent_app_date] => 2020-06-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5226
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17620342
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/620342 | Method of manufacturing semiconductor chips having a side wall sealing | Jun 17, 2020 | Issued |
Array
(
[id] => 16988813
[patent_doc_number] => 11076008
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-27
[patent_title] => Systems and methods for resolving ambiguous terms in social chatter based on a user profile
[patent_app_type] => utility
[patent_app_number] => 16/902754
[patent_app_country] => US
[patent_app_date] => 2020-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 22803
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16902754
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/902754 | Systems and methods for resolving ambiguous terms in social chatter based on a user profile | Jun 15, 2020 | Issued |
Array
(
[id] => 17745639
[patent_doc_number] => 11393720
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-19
[patent_title] => Die corner protection by using polymer deposition technology
[patent_app_type] => utility
[patent_app_number] => 16/901485
[patent_app_country] => US
[patent_app_date] => 2020-06-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 4482
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 122
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16901485
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/901485 | Die corner protection by using polymer deposition technology | Jun 14, 2020 | Issued |
Array
(
[id] => 18623737
[patent_doc_number] => 11756792
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Apparatus having integrated circuit well structures of vertical and/or retrograde profiles
[patent_app_type] => utility
[patent_app_number] => 16/899715
[patent_app_country] => US
[patent_app_date] => 2020-06-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 17
[patent_no_of_words] => 7360
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 177
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899715
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/899715 | Apparatus having integrated circuit well structures of vertical and/or retrograde profiles | Jun 11, 2020 | Issued |
Array
(
[id] => 17295457
[patent_doc_number] => 20210391296
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-16
[patent_title] => SELF-ALIGNED INTERCONNECT STRUCTURE
[patent_app_type] => utility
[patent_app_number] => 16/898670
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8570
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 241
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16898670
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/898670 | Self-aligned interconnect structure | Jun 10, 2020 | Issued |
Array
(
[id] => 18204088
[patent_doc_number] => 11586479
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-21
[patent_title] => Load balancing of computing sessions with load patterns
[patent_app_type] => utility
[patent_app_number] => 16/899098
[patent_app_country] => US
[patent_app_date] => 2020-06-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 19888
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 169
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16899098
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/899098 | Load balancing of computing sessions with load patterns | Jun 10, 2020 | Issued |
Array
(
[id] => 16332582
[patent_doc_number] => 20200303548
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-09-24
[patent_title] => METHOD OF FORMING SOURCE/DRAIN EPITAXIAL STACKS
[patent_app_type] => utility
[patent_app_number] => 16/895673
[patent_app_country] => US
[patent_app_date] => 2020-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6487
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16895673
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/895673 | Method of forming source/drain epitaxial stacks | Jun 7, 2020 | Issued |
Array
(
[id] => 16516094
[patent_doc_number] => 20200395352
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => MULTI-CHIP PACKAGING
[patent_app_type] => utility
[patent_app_number] => 16/892698
[patent_app_country] => US
[patent_app_date] => 2020-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 12790
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16892698
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/892698 | Multi-chip packaging | Jun 3, 2020 | Issued |
Array
(
[id] => 17279084
[patent_doc_number] => 20210385282
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-09
[patent_title] => Device-Level Network Switching
[patent_app_type] => utility
[patent_app_number] => 16/892526
[patent_app_country] => US
[patent_app_date] => 2020-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8466
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16892526
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/892526 | Device-level network switching | Jun 3, 2020 | Issued |
Array
(
[id] => 18054145
[patent_doc_number] => 11527540
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-13
[patent_title] => Implantations for forming source/drain regions of different transistors
[patent_app_type] => utility
[patent_app_number] => 16/891696
[patent_app_country] => US
[patent_app_date] => 2020-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 5600
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891696
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/891696 | Implantations for forming source/drain regions of different transistors | Jun 2, 2020 | Issued |
Array
(
[id] => 18481203
[patent_doc_number] => 11694958
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-07-04
[patent_title] => Layout design for threshold voltage tuning
[patent_app_type] => utility
[patent_app_number] => 16/891600
[patent_app_country] => US
[patent_app_date] => 2020-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 21
[patent_no_of_words] => 6677
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16891600
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/891600 | Layout design for threshold voltage tuning | Jun 2, 2020 | Issued |
Array
(
[id] => 17623309
[patent_doc_number] => 11342374
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-05-24
[patent_title] => Mechanisms for forming image-sensor device with deep-trench isolation structure
[patent_app_type] => utility
[patent_app_number] => 16/889161
[patent_app_country] => US
[patent_app_date] => 2020-06-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 9
[patent_no_of_words] => 4426
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16889161
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/889161 | Mechanisms for forming image-sensor device with deep-trench isolation structure | May 31, 2020 | Issued |
Array
(
[id] => 18190631
[patent_doc_number] => 11581232
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-02-14
[patent_title] => Semiconductor device with a dielectric between portions
[patent_app_type] => utility
[patent_app_number] => 16/880684
[patent_app_country] => US
[patent_app_date] => 2020-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 20
[patent_no_of_words] => 7997
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16880684
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/880684 | Semiconductor device with a dielectric between portions | May 20, 2020 | Issued |
Array
(
[id] => 18088631
[patent_doc_number] => 11538770
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-12-27
[patent_title] => Semiconductor package including passive device embedded therein and method of manufacturing the same
[patent_app_type] => utility
[patent_app_number] => 16/878727
[patent_app_country] => US
[patent_app_date] => 2020-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 14
[patent_no_of_words] => 9140
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 205
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16878727
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/878727 | Semiconductor package including passive device embedded therein and method of manufacturing the same | May 19, 2020 | Issued |
Array
(
[id] => 19980312
[patent_doc_number] => 12347800
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-07-01
[patent_title] => Method of fabricating a conductive layer on an IC using non-lithographic fabrication techniques
[patent_app_type] => utility
[patent_app_number] => 17/611614
[patent_app_country] => US
[patent_app_date] => 2020-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 17
[patent_no_of_words] => 1710
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17611614
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/611614 | Method of fabricating a conductive layer on an IC using non-lithographic fabrication techniques | May 18, 2020 | Issued |
Array
(
[id] => 17758198
[patent_doc_number] => 11398497
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-07-26
[patent_title] => Three-dimensional memory device containing auxiliary support pillar structures and method of making the same
[patent_app_type] => utility
[patent_app_number] => 16/876370
[patent_app_country] => US
[patent_app_date] => 2020-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 44
[patent_figures_cnt] => 61
[patent_no_of_words] => 17856
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16876370
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/876370 | Three-dimensional memory device containing auxiliary support pillar structures and method of making the same | May 17, 2020 | Issued |