Natalie K. Walford

Array ( [id] => 18611342 [patent_doc_number] => 20230278073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-07 [patent_title] => SEMICONDUCTOR DEVICE WITH IMPROVED DIELECTRIC FILM STRUCTURE AND METHOD OF MANUFACTURING SAME [patent_app_type] => utility [patent_app_number] => 17/688042 [patent_app_country] => US [patent_app_date] => 2022-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9817 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17688042 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17855402 [patent_doc_number] => 20220285445 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-08 [patent_title] => DISPLAY PANEL AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/686934 [patent_app_country] => US [patent_app_date] => 2022-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 29083 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17686934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18601819 [patent_doc_number] => 20230276624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-31 [patent_title] => ELECTRONIC DEVICES INCLUDING PILLARS INCLUDING A MEMORY MATERIAL, AND RELATED MEMORY DEVICES, SYSTEMS, AND METHODS [patent_app_type] => utility [patent_app_number] => 17/682514 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19161115 [patent_doc_number] => 20240153822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => SEMICONDUCTOR CHIP MANUFACTURING METHOD AND SUBSTRATE PROCESSING APPARATUS [patent_app_type] => utility [patent_app_number] => 18/549610 [patent_app_country] => US [patent_app_date] => 2022-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18549610 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19191422 [patent_doc_number] => 20240170335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => GALLIUM OXIDE SUBSTRATE DIVISION METHOD [patent_app_type] => utility [patent_app_number] => 18/549255 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18549255 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19957382 [patent_doc_number] => 12327801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-10 [patent_title] => Robust mold integrated substrate [patent_app_type] => utility [patent_app_number] => 17/669265 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 31 [patent_no_of_words] => 7374 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17669265 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983631 [patent_doc_number] => 11908820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => Dual solder methodologies for ultrahigh density first level interconnections [patent_app_type] => utility [patent_app_number] => 17/668246 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 8692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20484190 [patent_doc_number] => 12532671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2026-01-20 [patent_title] => Superconducting vias for routing electrical signals through substrates and their methods of manufacture [patent_app_type] => utility [patent_app_number] => 17/667720 [patent_app_country] => US [patent_app_date] => 2022-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 10796 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17667720 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18206277 [patent_doc_number] => 11588689 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-02-21 [patent_title] => Migrating software defined network [patent_app_type] => utility [patent_app_number] => 17/592459 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 9921 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17592459 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17615523 [patent_doc_number] => 20220157803 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-19 [patent_title] => MULTI-CHIP PACKAGING [patent_app_type] => utility [patent_app_number] => 17/587657 [patent_app_country] => US [patent_app_date] => 2022-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17587657 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18533247 [patent_doc_number] => 20230238323 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-27 [patent_title] => INTERCONNECT STRUCTURE INCLUDING VERTICALLY STACKED POWER AND GROUND LINES [patent_app_type] => utility [patent_app_number] => 17/585351 [patent_app_country] => US [patent_app_date] => 2022-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17585351 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17583288 [patent_doc_number] => 20220140143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => DEVICE ISOLATION [patent_app_type] => utility [patent_app_number] => 17/578699 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14789 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17578699 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19679390 [patent_doc_number] => 12191263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Semiconductor structure and manufacturing method of semiconductor structure [patent_app_type] => utility [patent_app_number] => 17/648130 [patent_app_country] => US [patent_app_date] => 2022-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5076 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648130 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17566854 [patent_doc_number] => 20220131003 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => MEMORY ARRAYS WITH VERTICAL TRANSISTORS AND THE FORMATION THEREOF [patent_app_type] => utility [patent_app_number] => 17/568133 [patent_app_country] => US [patent_app_date] => 2022-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11524 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17568133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17566599 [patent_doc_number] => 20220130748 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHODS OF EMBEDDING MAGNETIC STRUCTURES IN SUBSTRATES [patent_app_type] => utility [patent_app_number] => 17/567639 [patent_app_country] => US [patent_app_date] => 2022-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9633 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17567639 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18859194 [patent_doc_number] => 11856804 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Imaging display device and electronic device [patent_app_type] => utility [patent_app_number] => 17/563187 [patent_app_country] => US [patent_app_date] => 2021-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 57 [patent_no_of_words] => 30409 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17563187 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17536929 [patent_doc_number] => 20220115538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => SEMICONDUCTOR DEVICES HAVING STRESSED ACTIVE REGIONS THEREIN AND METHODS OF FORMING SAME [patent_app_type] => utility [patent_app_number] => 17/558915 [patent_app_country] => US [patent_app_date] => 2021-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17558915 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18456331 [patent_doc_number] => 20230197613 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => REPLACEMENT VIA AND BURIED OR BACKSIDE POWER RAIL [patent_app_type] => utility [patent_app_number] => 17/556414 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12440 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17556414 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18983751 [patent_doc_number] => 11908941 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-20 [patent_title] => FinFET transistor [patent_app_type] => utility [patent_app_number] => 17/551712 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7768 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17551712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17661376 [patent_doc_number] => 20220181841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => MANUFACTURABLE LASER DIODES ON A LARGE AREA GALLIUM AND NITROGEN CONTAINING SUBSTRATE [patent_app_type] => utility [patent_app_number] => 17/552261 [patent_app_country] => US [patent_app_date] => 2021-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 32488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17552261 [rel_patent_id] =>[rel_patent_doc_number] =>)