Natasha W Cosme
Examiner (ID: 4117, Phone: (571)270-7225 , Office: P/2465 )
Most Active Art Unit | 2465 |
Art Unit(s) | 2465, 2645, 2641, 2617 |
Total Applications | 659 |
Issued Applications | 486 |
Pending Applications | 57 |
Abandoned Applications | 116 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 9023250
[patent_doc_number] => 08533245
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-09-10
[patent_title] => 'Multipliers with a reduced number of memory blocks'
[patent_app_type] => utility
[patent_app_number] => 12/716280
[patent_app_country] => US
[patent_app_date] => 2010-03-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3837
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 97
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716280
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/716280 | Multipliers with a reduced number of memory blocks | Mar 2, 2010 | Issued |
Array
(
[id] => 8645416
[patent_doc_number] => 08370413
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-02-05
[patent_title] => 'No-multiply finite impulse response (FIR) filter using phase additions'
[patent_app_type] => utility
[patent_app_number] => 12/715584
[patent_app_country] => US
[patent_app_date] => 2010-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4105
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12715584
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/715584 | No-multiply finite impulse response (FIR) filter using phase additions | Mar 1, 2010 | Issued |
Array
(
[id] => 8632639
[patent_doc_number] => 08364738
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2013-01-29
[patent_title] => 'Programmable logic device with specialized functional block'
[patent_app_type] => utility
[patent_app_number] => 12/715645
[patent_app_country] => US
[patent_app_date] => 2010-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 5565
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 184
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12715645
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/715645 | Programmable logic device with specialized functional block | Mar 1, 2010 | Issued |
Array
(
[id] => 9115952
[patent_doc_number] => 08572144
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-10-29
[patent_title] => 'Signal mapping'
[patent_app_type] => utility
[patent_app_number] => 12/716113
[patent_app_country] => US
[patent_app_date] => 2010-03-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 34
[patent_figures_cnt] => 35
[patent_no_of_words] => 11028
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12716113
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/716113 | Signal mapping | Mar 1, 2010 | Issued |
Array
(
[id] => 8786881
[patent_doc_number] => 08433736
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-04-30
[patent_title] => 'Scalable Montgomery multiplication architecture'
[patent_app_type] => utility
[patent_app_number] => 12/714992
[patent_app_country] => US
[patent_app_date] => 2010-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 19
[patent_no_of_words] => 8032
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 356
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12714992
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/714992 | Scalable Montgomery multiplication architecture | Feb 28, 2010 | Issued |
Array
(
[id] => 8678412
[patent_doc_number] => 08386546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2013-02-26
[patent_title] => 'Montgomery multiplication architecture'
[patent_app_type] => utility
[patent_app_number] => 12/714987
[patent_app_country] => US
[patent_app_date] => 2010-03-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 19
[patent_no_of_words] => 6480
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 351
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12714987
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/714987 | Montgomery multiplication architecture | Feb 28, 2010 | Issued |
Array
(
[id] => 6051862
[patent_doc_number] => 20110208794
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-08-25
[patent_title] => 'COMPUTING HALF INSTRUCTIONS OF FLOATING POINT NUMBERS WITHOUT EARLY ADJUSTMENT OF THE SOURCE OPERANDS'
[patent_app_type] => utility
[patent_app_number] => 12/712618
[patent_app_country] => US
[patent_app_date] => 2010-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 8961
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0208/20110208794.pdf
[firstpage_image] =>[orig_patent_app_number] => 12712618
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/712618 | Computing half instructions of floating point numbers without early adjustment of the source operands | Feb 24, 2010 | Issued |
Array
(
[id] => 8297210
[patent_doc_number] => 08225009
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-07-17
[patent_title] => 'Systems and methods for selectively discovering storage devices connected to host computing devices'
[patent_app_type] => utility
[patent_app_number] => 12/713164
[patent_app_country] => US
[patent_app_date] => 2010-02-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 9376
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12713164
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/713164 | Systems and methods for selectively discovering storage devices connected to host computing devices | Feb 24, 2010 | Issued |
Array
(
[id] => 8213753
[patent_doc_number] => 20120131229
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-24
[patent_title] => 'INPUT COMMAND'
[patent_app_type] => utility
[patent_app_number] => 13/387330
[patent_app_country] => US
[patent_app_date] => 2010-02-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6343
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0131/20120131229.pdf
[firstpage_image] =>[orig_patent_app_number] => 13387330
[rel_patent_id] =>[rel_patent_doc_number] =>) 13/387330 | Input command | Feb 10, 2010 | Issued |
Array
(
[id] => 6182482
[patent_doc_number] => 20110179413
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2011-07-21
[patent_title] => 'Guest/Hypervisor Interrupt Coalescing for Storage Adapter Virtual Function in Guest Passthrough Mode'
[patent_app_type] => utility
[patent_app_number] => 12/687999
[patent_app_country] => US
[patent_app_date] => 2010-01-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 9160
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0179/20110179413.pdf
[firstpage_image] =>[orig_patent_app_number] => 12687999
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/687999 | Guest/hypervisor interrupt coalescing for storage adapter virtual function in guest passthrough mode | Jan 14, 2010 | Issued |
Array
(
[id] => 7982465
[patent_doc_number] => 08073991
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-12-06
[patent_title] => 'Isolated HART interface with programmable data flow'
[patent_app_type] => utility
[patent_app_number] => 12/687485
[patent_app_country] => US
[patent_app_date] => 2010-01-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5194
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 174
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/08/073/08073991.pdf
[firstpage_image] =>[orig_patent_app_number] => 12687485
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/687485 | Isolated HART interface with programmable data flow | Jan 13, 2010 | Issued |
Array
(
[id] => 6651229
[patent_doc_number] => 20100228889
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-09-09
[patent_title] => 'INFORMATION PROCESSING APPARATUS AND STORAGE DEVICE CONTROL METHOD'
[patent_app_type] => utility
[patent_app_number] => 12/684029
[patent_app_country] => US
[patent_app_date] => 2010-01-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 3605
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0228/20100228889.pdf
[firstpage_image] =>[orig_patent_app_number] => 12684029
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/684029 | Information processing apparatus and storage device control method | Jan 6, 2010 | Issued |
Array
(
[id] => 6465236
[patent_doc_number] => 20100281479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-11-04
[patent_title] => 'Systems and Methods for Input/Output Isolation'
[patent_app_type] => utility
[patent_app_number] => 12/652264
[patent_app_country] => US
[patent_app_date] => 2010-01-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 5747
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0281/20100281479.pdf
[firstpage_image] =>[orig_patent_app_number] => 12652264
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/652264 | Systems and methods for input/output isolation | Jan 4, 2010 | Issued |
Array
(
[id] => 6646334
[patent_doc_number] => 20100174833
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-07-08
[patent_title] => 'Method and Apparatus for Identifying a Device Handle in a Computer System'
[patent_app_type] => utility
[patent_app_number] => 12/650887
[patent_app_country] => US
[patent_app_date] => 2009-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 10962
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0174/20100174833.pdf
[firstpage_image] =>[orig_patent_app_number] => 12650887
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/650887 | Method and apparatus for identifying a device handle in a computer system | Dec 30, 2009 | Issued |
Array
(
[id] => 7684120
[patent_doc_number] => 20100122021
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-05-13
[patent_title] => 'USB-Attached-SCSI Flash-Memory System with Additional Command, Status, and Control Pipes to a Smart-Storage Switch'
[patent_app_type] => utility
[patent_app_number] => 12/651334
[patent_app_country] => US
[patent_app_date] => 2009-12-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 33
[patent_no_of_words] => 13077
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0122/20100122021.pdf
[firstpage_image] =>[orig_patent_app_number] => 12651334
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/651334 | USB-attached-SCSI flash-memory system with additional command, status, and control pipes to a smart-storage switch | Dec 30, 2009 | Issued |
Array
(
[id] => 9378807
[patent_doc_number] => 08683089
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2014-03-25
[patent_title] => 'Method and apparatus for equalizing a bandwidth impedance mismatch between a client and an interface'
[patent_app_type] => utility
[patent_app_number] => 12/650371
[patent_app_country] => US
[patent_app_date] => 2009-12-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8202
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12650371
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/650371 | Method and apparatus for equalizing a bandwidth impedance mismatch between a client and an interface | Dec 29, 2009 | Issued |
Array
(
[id] => 9326130
[patent_doc_number] => 08661167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'DMA (direct memory access) coalescing'
[patent_app_type] => utility
[patent_app_number] => 12/655311
[patent_app_country] => US
[patent_app_date] => 2009-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4402
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12655311
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/655311 | DMA (direct memory access) coalescing | Dec 28, 2009 | Issued |
Array
(
[id] => 9326130
[patent_doc_number] => 08661167
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2014-02-25
[patent_title] => 'DMA (direct memory access) coalescing'
[patent_app_type] => utility
[patent_app_number] => 12/655311
[patent_app_country] => US
[patent_app_date] => 2009-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 4402
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12655311
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/655311 | DMA (direct memory access) coalescing | Dec 28, 2009 | Issued |
Array
(
[id] => 6628318
[patent_doc_number] => 20100100681
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'System on a chip for networking'
[patent_app_type] => utility
[patent_app_number] => 12/642736
[patent_app_country] => US
[patent_app_date] => 2009-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 9791
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20100100681.pdf
[firstpage_image] =>[orig_patent_app_number] => 12642736
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/642736 | System on a chip for networking | Dec 17, 2009 | Issued |
Array
(
[id] => 6628025
[patent_doc_number] => 20100100651
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2010-04-22
[patent_title] => 'Multipurpose and programmable pad for an integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 12/654345
[patent_app_country] => US
[patent_app_date] => 2009-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 15
[patent_no_of_words] => 5924
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0100/20100100651.pdf
[firstpage_image] =>[orig_patent_app_number] => 12654345
[rel_patent_id] =>[rel_patent_doc_number] =>) 12/654345 | Multipurpose and programmable pad for an integrated circuit | Dec 16, 2009 | Issued |