Nathan Erb

Array ( [id] => 3947288 [patent_doc_number] => 05981997 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Horizontal field effect transistor and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/821460 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2963 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/981/05981997.pdf [firstpage_image] =>[orig_patent_app_number] => 821460 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4002603 [patent_doc_number] => 05923055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-13 [patent_title] => 'Controllable semiconductor component' [patent_app_type] => 1 [patent_app_number] => 8/809848 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 10889 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 361 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/923/05923055.pdf [firstpage_image] =>[orig_patent_app_number] => 809848 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3933009 [patent_doc_number] => 05877528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Structure to provide effective channel-stop in termination areas for trenched power transistors' [patent_app_type] => 1 [patent_app_number] => 8/810546 [patent_app_country] => US [patent_app_date] => 1997-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 4289 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877528.pdf [firstpage_image] =>[orig_patent_app_number] => 810546 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3879083 [patent_doc_number] => 05763922 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'CMOS integrated circuit having PMOS and NMOS devices with different gate dielectric layers' [patent_app_type] => 1 [patent_app_number] => 8/810682 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 4832 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/763/05763922.pdf [firstpage_image] =>[orig_patent_app_number] => 810682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845332 [patent_doc_number] => 05744836 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Insulating gate type field effect transistor' [patent_app_type] => 1 [patent_app_number] => 8/808170 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744836.pdf [firstpage_image] =>[orig_patent_app_number] => 808170 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3836887 [patent_doc_number] => 05814860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Semiconductor IC device having first and second pads on surface of semiconductor chip' [patent_app_type] => 1 [patent_app_number] => 8/804828 [patent_app_country] => US [patent_app_date] => 1997-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 3782 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/814/05814860.pdf [firstpage_image] =>[orig_patent_app_number] => 804828 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4027166 [patent_doc_number] => 05925923 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Merged single polysilicon bipolar NPN transistor' [patent_app_type] => 1 [patent_app_number] => 8/803122 [patent_app_country] => US [patent_app_date] => 1997-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 1326 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/925/05925923.pdf [firstpage_image] =>[orig_patent_app_number] => 803122 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3835913 [patent_doc_number] => 05739578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'High power transistor with contact plugs extended from collectors through a substrate to have ends connected together in an indent in the substrate' [patent_app_type] => 1 [patent_app_number] => 8/800376 [patent_app_country] => US [patent_app_date] => 1997-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2084 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739578.pdf [firstpage_image] =>[orig_patent_app_number] => 800376 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3845463 [patent_doc_number] => 05744845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-28 [patent_title] => 'Complementary MOS field effect transistor with tunnel effect means' [patent_app_type] => 1 [patent_app_number] => 8/800147 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 32 [patent_no_of_words] => 6918 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/744/05744845.pdf [firstpage_image] =>[orig_patent_app_number] => 800147 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3835624 [patent_doc_number] => 05739559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'Compound semiconductor integrated circuit with a particular high resistance layer' [patent_app_type] => 1 [patent_app_number] => 8/798450 [patent_app_country] => US [patent_app_date] => 1997-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 5253 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739559.pdf [firstpage_image] =>[orig_patent_app_number] => 798450 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4049298 [patent_doc_number] => 05912496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Semiconductor device having power MOS transistor including parasitic transistor' [patent_app_type] => 1 [patent_app_number] => 8/795630 [patent_app_country] => US [patent_app_date] => 1997-02-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4509 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/912/05912496.pdf [firstpage_image] =>[orig_patent_app_number] => 795630 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3780269 [patent_doc_number] => 05808344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-15 [patent_title] => 'Single-transistor logic and CMOS inverters' [patent_app_type] => 1 [patent_app_number] => 8/795714 [patent_app_country] => US [patent_app_date] => 1997-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3078 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/808/05808344.pdf [firstpage_image] =>[orig_patent_app_number] => 795714 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3835809 [patent_doc_number] => 05739572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'High voltage semiconductor device' [patent_app_type] => 1 [patent_app_number] => 8/794644 [patent_app_country] => US [patent_app_date] => 1997-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 26 [patent_no_of_words] => 9427 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739572.pdf [firstpage_image] =>[orig_patent_app_number] => 794644 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3931796 [patent_doc_number] => 05952696 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-14 [patent_title] => 'Complementary metal oxide semiconductor device with selective doping' [patent_app_type] => 1 [patent_app_number] => 8/792196 [patent_app_country] => US [patent_app_date] => 1997-01-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 21 [patent_no_of_words] => 4263 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 17 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/952/05952696.pdf [firstpage_image] =>[orig_patent_app_number] => 792196 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4179830 [patent_doc_number] => 06084278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'MOSFET with gradiently doped polysilicon gate electrode' [patent_app_type] => 1 [patent_app_number] => 8/791030 [patent_app_country] => US [patent_app_date] => 1997-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3485 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/084/06084278.pdf [firstpage_image] =>[orig_patent_app_number] => 791030 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3932796 [patent_doc_number] => 05877513 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => 1 [patent_app_number] => 8/788561 [patent_app_country] => US [patent_app_date] => 1997-01-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 3989 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877513.pdf [firstpage_image] =>[orig_patent_app_number] => 788561 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3835610 [patent_doc_number] => 05739558 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-14 [patent_title] => 'High electron mobility transistor including asymmetrical carrier supply layers sandwiching a channel layer' [patent_app_type] => 1 [patent_app_number] => 8/786210 [patent_app_country] => US [patent_app_date] => 1997-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 21 [patent_no_of_words] => 12202 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/739/05739558.pdf [firstpage_image] =>[orig_patent_app_number] => 786210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882579 [patent_doc_number] => 05747855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'CMOS integrated circuitry with Halo and LDD regions' [patent_app_type] => 1 [patent_app_number] => 8/782248 [patent_app_country] => US [patent_app_date] => 1997-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2487 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/747/05747855.pdf [firstpage_image] =>[orig_patent_app_number] => 782248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3938579 [patent_doc_number] => 05939736 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Insulated gate thyristor' [patent_app_type] => 1 [patent_app_number] => 8/779514 [patent_app_country] => US [patent_app_date] => 1997-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 67 [patent_no_of_words] => 19391 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 225 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/939/05939736.pdf [firstpage_image] =>[orig_patent_app_number] => 779514 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4067805 [patent_doc_number] => 05895957 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-20 [patent_title] => 'Minimum charge FET fabricated on an ultrathin silicon on sapphire wafer' [patent_app_type] => 1 [patent_app_number] => 8/778669 [patent_app_country] => US [patent_app_date] => 1997-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9025 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/895/05895957.pdf [firstpage_image] =>[orig_patent_app_number] => 778669 [rel_patent_id] =>[rel_patent_doc_number] =>)