| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3954422
[patent_doc_number] => 05977637
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-02
[patent_title] => 'Integrated electronic device having flip-chip connection with circuit board'
[patent_app_type] => 1
[patent_app_number] => 8/769529
[patent_app_country] => US
[patent_app_date] => 1996-12-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 25
[patent_no_of_words] => 3581
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 114
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/977/05977637.pdf
[firstpage_image] =>[orig_patent_app_number] => 769529
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/769529 | Integrated electronic device having flip-chip connection with circuit board | Dec 18, 1996 | Issued |
Array
(
[id] => 3891796
[patent_doc_number] => 05714799
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-02-03
[patent_title] => 'Resin-sealed type semiconductor device having an unoccupied second die pad'
[patent_app_type] => 1
[patent_app_number] => 8/768920
[patent_app_country] => US
[patent_app_date] => 1996-12-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 9
[patent_no_of_words] => 2228
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/714/05714799.pdf
[firstpage_image] =>[orig_patent_app_number] => 768920
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768920 | Resin-sealed type semiconductor device having an unoccupied second die pad | Dec 17, 1996 | Issued |
Array
(
[id] => 3943597
[patent_doc_number] => 05872397
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-16
[patent_title] => 'Semiconductor device package including a thick integrated circuit chip stack'
[patent_app_type] => 1
[patent_app_number] => 8/768363
[patent_app_country] => US
[patent_app_date] => 1996-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 6
[patent_no_of_words] => 3156
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 175
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/872/05872397.pdf
[firstpage_image] =>[orig_patent_app_number] => 768363
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/768363 | Semiconductor device package including a thick integrated circuit chip stack | Dec 16, 1996 | Issued |
Array
(
[id] => 4037978
[patent_doc_number] => 05994742
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-30
[patent_title] => 'Plasma emission triggered protection device for protecting against charge-induced damage'
[patent_app_type] => 1
[patent_app_number] => 8/759588
[patent_app_country] => US
[patent_app_date] => 1996-12-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 12
[patent_no_of_words] => 4193
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 216
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/994/05994742.pdf
[firstpage_image] =>[orig_patent_app_number] => 759588
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759588 | Plasma emission triggered protection device for protecting against charge-induced damage | Dec 4, 1996 | Issued |
Array
(
[id] => 3950470
[patent_doc_number] => 05990545
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-11-23
[patent_title] => 'Chip scale ball grid array for integrated circuit package'
[patent_app_type] => 1
[patent_app_number] => 8/759253
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 7507
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 90
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/990/05990545.pdf
[firstpage_image] =>[orig_patent_app_number] => 759253
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759253 | Chip scale ball grid array for integrated circuit package | Dec 1, 1996 | Issued |
Array
(
[id] => 3748240
[patent_doc_number] => 05801433
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-09-01
[patent_title] => 'Semiconductor device with smaller package'
[patent_app_type] => 1
[patent_app_number] => 8/759007
[patent_app_country] => US
[patent_app_date] => 1996-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 33
[patent_no_of_words] => 7189
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 273
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/801/05801433.pdf
[firstpage_image] =>[orig_patent_app_number] => 759007
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/759007 | Semiconductor device with smaller package | Dec 1, 1996 | Issued |
Array
(
[id] => 3821023
[patent_doc_number] => 05789816
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-08-04
[patent_title] => 'Multiple-chip integrated circuit package including a dummy chip'
[patent_app_type] => 1
[patent_app_number] => 8/749779
[patent_app_country] => US
[patent_app_date] => 1996-11-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 1582
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/789/05789816.pdf
[firstpage_image] =>[orig_patent_app_number] => 749779
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/749779 | Multiple-chip integrated circuit package including a dummy chip | Nov 14, 1996 | Issued |
Array
(
[id] => 3998078
[patent_doc_number] => 05892245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-04-06
[patent_title] => 'Ball grid array package emulator'
[patent_app_type] => 1
[patent_app_number] => 8/751534
[patent_app_country] => US
[patent_app_date] => 1996-11-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 2626
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/892/05892245.pdf
[firstpage_image] =>[orig_patent_app_number] => 751534
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/751534 | Ball grid array package emulator | Nov 10, 1996 | Issued |
| 08/741809 | MICROWAVE INTEGRATED CIRCUIT | Oct 30, 1996 | Abandoned |
Array
(
[id] => 3791130
[patent_doc_number] => 05736784
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-04-07
[patent_title] => 'Variable-width lead interconnection structure and method'
[patent_app_type] => 1
[patent_app_number] => 8/740595
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 1559
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 62
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/736/05736784.pdf
[firstpage_image] =>[orig_patent_app_number] => 740595
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/740595 | Variable-width lead interconnection structure and method | Oct 30, 1996 | Issued |
Array
(
[id] => 3630005
[patent_doc_number] => 05621245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-04-15
[patent_title] => 'Apparatus for optimizing operating parameters of an integrated circuit package having a voltage regulator mounted thereon'
[patent_app_type] => 1
[patent_app_number] => 8/741526
[patent_app_country] => US
[patent_app_date] => 1996-10-31
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 2574
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 80
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/621/05621245.pdf
[firstpage_image] =>[orig_patent_app_number] => 741526
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/741526 | Apparatus for optimizing operating parameters of an integrated circuit package having a voltage regulator mounted thereon | Oct 30, 1996 | Issued |
Array
(
[id] => 3705594
[patent_doc_number] => 05646421
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-07-08
[patent_title] => 'Multicolor voltage tunable quantum well intersubband infrared photodetector'
[patent_app_type] => 1
[patent_app_number] => 8/735314
[patent_app_country] => US
[patent_app_date] => 1996-10-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2256
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/646/05646421.pdf
[firstpage_image] =>[orig_patent_app_number] => 735314
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/735314 | Multicolor voltage tunable quantum well intersubband infrared photodetector | Oct 24, 1996 | Issued |
Array
(
[id] => 4301489
[patent_doc_number] => 06184587
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-02-06
[patent_title] => 'Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic components'
[patent_app_type] => 1
[patent_app_number] => 8/735815
[patent_app_country] => US
[patent_app_date] => 1996-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 38
[patent_no_of_words] => 19942
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 71
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/184/06184587.pdf
[firstpage_image] =>[orig_patent_app_number] => 735815
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/735815 | Resilient contact structures, electronic interconnection component, and method of mounting resilient contact structures to electronic components | Oct 20, 1996 | Issued |
| 08/734417 | MULTILEVEL INTERCONNECTION STRUCTURE FOR INTEGRATED CIRCUITS AND METHOD OF PRODUCING SAME | Oct 15, 1996 | Abandoned |
Array
(
[id] => 3954524
[patent_doc_number] => 05955762
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-09-21
[patent_title] => 'Microelectronic package with polymer ESD protection'
[patent_app_type] => 1
[patent_app_number] => 8/723140
[patent_app_country] => US
[patent_app_date] => 1996-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 10
[patent_no_of_words] => 4680
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/955/05955762.pdf
[firstpage_image] =>[orig_patent_app_number] => 723140
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/723140 | Microelectronic package with polymer ESD protection | Sep 30, 1996 | Issued |
Array
(
[id] => 4054362
[patent_doc_number] => 05869888
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-02-09
[patent_title] => 'Semiconductor device with lead structure on principal surface of chip'
[patent_app_type] => 1
[patent_app_number] => 8/721339
[patent_app_country] => US
[patent_app_date] => 1996-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 43
[patent_no_of_words] => 8704
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 277
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/869/05869888.pdf
[firstpage_image] =>[orig_patent_app_number] => 721339
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721339 | Semiconductor device with lead structure on principal surface of chip | Sep 25, 1996 | Issued |
Array
(
[id] => 4137285
[patent_doc_number] => 06034422
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-03-07
[patent_title] => 'Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame'
[patent_app_type] => 1
[patent_app_number] => 8/721265
[patent_app_country] => US
[patent_app_date] => 1996-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 14685
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/034/06034422.pdf
[firstpage_image] =>[orig_patent_app_number] => 721265
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/721265 | Lead frame, method for partial noble plating of said lead frame and semiconductor device having said lead frame | Sep 25, 1996 | Issued |
Array
(
[id] => 3692558
[patent_doc_number] => 05691574
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-11-25
[patent_title] => 'Semiconductor device capable of high speed operation and being integrated with high density'
[patent_app_type] => 1
[patent_app_number] => 8/719586
[patent_app_country] => US
[patent_app_date] => 1996-09-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 8
[patent_no_of_words] => 2604
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/691/05691574.pdf
[firstpage_image] =>[orig_patent_app_number] => 719586
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/719586 | Semiconductor device capable of high speed operation and being integrated with high density | Sep 24, 1996 | Issued |
Array
(
[id] => 3893252
[patent_doc_number] => 05723909
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-03
[patent_title] => 'Semiconductor device and associated fabrication method'
[patent_app_type] => 1
[patent_app_number] => 8/712237
[patent_app_country] => US
[patent_app_date] => 1996-09-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 23
[patent_no_of_words] => 5332
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/723/05723909.pdf
[firstpage_image] =>[orig_patent_app_number] => 712237
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/712237 | Semiconductor device and associated fabrication method | Sep 10, 1996 | Issued |
Array
(
[id] => 3883212
[patent_doc_number] => 05729029
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1998-03-17
[patent_title] => 'Maximizing electrical doping while reducing material cracking in III-V nitride semiconductor devices'
[patent_app_type] => 1
[patent_app_number] => 8/709355
[patent_app_country] => US
[patent_app_date] => 1996-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 1858
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/729/05729029.pdf
[firstpage_image] =>[orig_patent_app_number] => 709355
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/709355 | Maximizing electrical doping while reducing material cracking in III-V nitride semiconductor devices | Sep 5, 1996 | Issued |