Nathan K. Kelley

Array ( [id] => 3821136 [patent_doc_number] => 05770867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Photocoupler device with light-transmissive resin including fillers and a producing process thereof' [patent_app_type] => 1 [patent_app_number] => 8/585503 [patent_app_country] => US [patent_app_date] => 1996-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3930 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/770/05770867.pdf [firstpage_image] =>[orig_patent_app_number] => 585503 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3943610 [patent_doc_number] => 05872398 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-16 [patent_title] => 'Reduced stress LOC assembly including cantilevered leads' [patent_app_type] => 1 [patent_app_number] => 8/584738 [patent_app_country] => US [patent_app_date] => 1996-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 4616 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/872/05872398.pdf [firstpage_image] =>[orig_patent_app_number] => 584738 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3668784 [patent_doc_number] => 05668394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-16 [patent_title] => 'Prevention of fluorine-induced gate oxide degradation in WSi polycide structure' [patent_app_type] => 1 [patent_app_number] => 8/582599 [patent_app_country] => US [patent_app_date] => 1996-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1564 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/668/05668394.pdf [firstpage_image] =>[orig_patent_app_number] => 582599 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3933331 [patent_doc_number] => 05877549 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-03-02 [patent_title] => 'UFBGA package equipped with interface assembly including a photosoluble layer' [patent_app_type] => 1 [patent_app_number] => 8/581956 [patent_app_country] => US [patent_app_date] => 1996-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1114 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/877/05877549.pdf [firstpage_image] =>[orig_patent_app_number] => 581956 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3666767 [patent_doc_number] => 05625223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-04-29 [patent_title] => 'Surface mounting type diode' [patent_app_type] => 1 [patent_app_number] => 8/577511 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2504 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 257 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/625/05625223.pdf [firstpage_image] =>[orig_patent_app_number] => 577511 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3831070 [patent_doc_number] => 05783855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Lateral transistor' [patent_app_type] => 1 [patent_app_number] => 8/577373 [patent_app_country] => US [patent_app_date] => 1995-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 20 [patent_no_of_words] => 4624 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/783/05783855.pdf [firstpage_image] =>[orig_patent_app_number] => 577373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3653308 [patent_doc_number] => 05640043 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'High voltage silicon diode with optimum placement of silicon-germanium layers' [patent_app_type] => 1 [patent_app_number] => 8/580071 [patent_app_country] => US [patent_app_date] => 1995-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 3777 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640043.pdf [firstpage_image] =>[orig_patent_app_number] => 580071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3882758 [patent_doc_number] => 05747867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-05 [patent_title] => 'Integrated circuit structure with interconnect formed along walls of silicon island' [patent_app_type] => 1 [patent_app_number] => 8/573359 [patent_app_country] => US [patent_app_date] => 1995-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2743 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/747/05747867.pdf [firstpage_image] =>[orig_patent_app_number] => 573359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3766429 [patent_doc_number] => 05844273 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-01 [patent_title] => 'Vertical semiconductor device and method of manufacturing the same' [patent_app_type] => 1 [patent_app_number] => 8/569449 [patent_app_country] => US [patent_app_date] => 1995-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3901 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/844/05844273.pdf [firstpage_image] =>[orig_patent_app_number] => 569449 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3520244 [patent_doc_number] => 05576575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-19 [patent_title] => 'Semiconductor conversion device' [patent_app_type] => 1 [patent_app_number] => 8/567796 [patent_app_country] => US [patent_app_date] => 1995-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4270 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/576/05576575.pdf [firstpage_image] =>[orig_patent_app_number] => 567796 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4070281 [patent_doc_number] => 05866952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-02 [patent_title] => 'High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate' [patent_app_type] => 1 [patent_app_number] => 8/565269 [patent_app_country] => US [patent_app_date] => 1995-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/866/05866952.pdf [firstpage_image] =>[orig_patent_app_number] => 565269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3710690 [patent_doc_number] => 05654576 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-05 [patent_title] => 'Post-titanium nitride mask ROM programming method and device manufactured thereby' [patent_app_type] => 1 [patent_app_number] => 8/559324 [patent_app_country] => US [patent_app_date] => 1995-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 4391 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/654/05654576.pdf [firstpage_image] =>[orig_patent_app_number] => 559324 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3530843 [patent_doc_number] => 05541451 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-30 [patent_title] => 'Packaged semiconductor device with external leads having anchor holes provided at polyamide/glass sealed regions' [patent_app_type] => 1 [patent_app_number] => 8/554105 [patent_app_country] => US [patent_app_date] => 1995-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2776 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/541/05541451.pdf [firstpage_image] =>[orig_patent_app_number] => 554105 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3729983 [patent_doc_number] => 05701032 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Integrated circuit package' [patent_app_type] => 1 [patent_app_number] => 8/552359 [patent_app_country] => US [patent_app_date] => 1995-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7547 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 277 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701032.pdf [firstpage_image] =>[orig_patent_app_number] => 552359 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 3624657 [patent_doc_number] => 05641988 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Multi-layered, integrated circuit package having reduced parasitic noise characteristics' [patent_app_type] => 1 [patent_app_number] => 8/549985 [patent_app_country] => US [patent_app_date] => 1995-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 4166 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/641/05641988.pdf [firstpage_image] =>[orig_patent_app_number] => 549985 [rel_patent_id] =>[rel_patent_doc_number] =>)