Search

Nathan Sadler

Examiner (ID: 7400)

Most Active Art Unit
2139
Art Unit(s)
2189, 2139
Total Applications
791
Issued Applications
554
Pending Applications
55
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20446806 [patent_doc_number] => 20260003528 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => TRAFFIC SCHEDULING CONTROL METHOD AND DEVICE BASED ON ZONED STORAGE DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/171635 [patent_app_country] => US [patent_app_date] => 2025-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19171635 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/171635
TRAFFIC SCHEDULING CONTROL METHOD AND DEVICE BASED ON ZONED STORAGE DEVICE, AND STORAGE MEDIUM Apr 6, 2025 Pending
Array ( [id] => 20070646 [patent_doc_number] => 20250208868 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-26 [patent_title] => POWER/AREA EFFICIENT ACCELERATION OF PROCESSOR-BASED ARTIFICIAL NEURAL NETWORK COMPUTATION [patent_app_type] => utility [patent_app_number] => 19/073656 [patent_app_country] => US [patent_app_date] => 2025-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19073656 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/073656
POWER/AREA EFFICIENT ACCELERATION OF PROCESSOR-BASED ARTIFICIAL NEURAL NETWORK COMPUTATION Mar 6, 2025 Pending
Array ( [id] => 20101780 [patent_doc_number] => 20250231716 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => COMMAND SCHEDULING FOR A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 19/025878 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19025878 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/025878
COMMAND SCHEDULING FOR A MEMORY SYSTEM Jan 15, 2025 Pending
Array ( [id] => 20380337 [patent_doc_number] => 20250362830 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-27 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 19/023386 [patent_app_country] => US [patent_app_date] => 2025-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19023386 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/023386
MEMORY SYSTEM AND OPERATING METHOD THEREOF Jan 15, 2025 Pending
Array ( [id] => 20310652 [patent_doc_number] => 20250328281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MEMORY SYSTEMS AND METHODS OF OPERATING MEMORY SYSTEMS, ELECTRONIC APPARATUSES, AND COMPUTER READABLE STORAGE MEDIUMS THEREOF [patent_app_type] => utility [patent_app_number] => 19/012168 [patent_app_country] => US [patent_app_date] => 2025-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5029 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19012168 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/012168
MEMORY SYSTEMS AND METHODS OF OPERATING MEMORY SYSTEMS, ELECTRONIC APPARATUSES, AND COMPUTER READABLE STORAGE MEDIUMS THEREOF Jan 6, 2025 Pending
Array ( [id] => 20101930 [patent_doc_number] => 20250231866 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => WEAR LEVELING SCHEMES BASED ON RANDOMIZED PARAMETERS [patent_app_type] => utility [patent_app_number] => 19/000372 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4848 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19000372 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/000372
WEAR LEVELING SCHEMES BASED ON RANDOMIZED PARAMETERS Dec 22, 2024 Pending
Array ( [id] => 19849007 [patent_doc_number] => 20250094358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING [patent_app_type] => utility [patent_app_number] => 18/966252 [patent_app_country] => US [patent_app_date] => 2024-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95402 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18966252 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/966252
METHODS AND APPARATUS TO REDUCE BANK PRESSURE USING AGGRESSIVE WRITE MERGING Dec 2, 2024 Pending
Array ( [id] => 20421894 [patent_doc_number] => 20250383979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-12-18 [patent_title] => STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/957010 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18957010 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/957010
STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF Nov 21, 2024 Pending
Array ( [id] => 20043277 [patent_doc_number] => 20250181499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-05 [patent_title] => MEMORY MAPPING SYSTEM FOR REDUCING DATA RETRIEVAL COST IN STORAGE CONSISTING OF MULTIPLE MEMORIES [patent_app_type] => utility [patent_app_number] => 18/942321 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18942321 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/942321
MEMORY MAPPING SYSTEM FOR REDUCING DATA RETRIEVAL COST IN STORAGE CONSISTING OF MULTIPLE MEMORIES Nov 7, 2024 Pending
Array ( [id] => 20716938 [patent_doc_number] => 12632188 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Initializing memory systems [patent_app_type] => utility [patent_app_number] => 18/941954 [patent_app_country] => US [patent_app_date] => 2024-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7238 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18941954 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/941954
INITIALIZING MEMORY SYSTEMS Nov 7, 2024 Issued
Array ( [id] => 20695524 [patent_doc_number] => 20260126936 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-05-07 [patent_title] => PROCESSING NAMESPACE RANGE INFORMATION BY A GLOBAL COORDINATOR [patent_app_type] => utility [patent_app_number] => 18/938523 [patent_app_country] => US [patent_app_date] => 2024-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2307 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18938523 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/938523
PROCESSING NAMESPACE RANGE INFORMATION BY A GLOBAL COORDINATOR Nov 5, 2024 Pending
Array ( [id] => 20009671 [patent_doc_number] => 20250147893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => CACHE EVICT DUPLICATION MANAGEMENT [patent_app_type] => utility [patent_app_number] => 18/937091 [patent_app_country] => US [patent_app_date] => 2024-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18937091 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/937091
CACHE EVICT DUPLICATION MANAGEMENT Nov 4, 2024 Pending
Array ( [id] => 20251771 [patent_doc_number] => 20250300640 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => LATCH CIRCUIT WITH REDUCED PROPAGATION DELAY [patent_app_type] => utility [patent_app_number] => 18/929080 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3644 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18929080 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/929080
LATCH CIRCUIT WITH REDUCED PROPAGATION DELAY Oct 27, 2024 Pending
Array ( [id] => 20570666 [patent_doc_number] => 20260064591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-05 [patent_title] => DATA ERASE USING A MAPPING TABLE UPDATE IN A HOST DEVICE WITH FLASH MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/821327 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8202 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821327 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821327
DATA ERASE USING A MAPPING TABLE UPDATE IN A HOST DEVICE WITH FLASH MEMORY SYSTEM Aug 29, 2024 Pending
Array ( [id] => 20009670 [patent_doc_number] => 20250147892 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-08 [patent_title] => STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/819398 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9756 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819398 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/819398
STORAGE CONTROLLER, STORAGE DEVICE INCLUDING THE SAME, AND METHOD OF OPERATING STORAGE DEVICE Aug 28, 2024 Pending
Array ( [id] => 19878613 [patent_doc_number] => 20250110870 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-03 [patent_title] => MEMORY SYSTEM AND HOST DEVICE [patent_app_type] => utility [patent_app_number] => 18/820110 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820110 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820110
MEMORY SYSTEM AND HOST DEVICE Aug 28, 2024 Pending
Array ( [id] => 19633260 [patent_doc_number] => 20240411709 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => PROCESSOR AND MEMORY COMMUNICATION IN A STACKED MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/810657 [patent_app_country] => US [patent_app_date] => 2024-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 26079 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18810657 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/810657
PROCESSOR AND MEMORY COMMUNICATION IN A STACKED MEMORY SYSTEM Aug 20, 2024 Pending
Array ( [id] => 20461039 [patent_doc_number] => 20260010467 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-08 [patent_title] => MEMORY CAPACITY ADJUSTMENT METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/137256 [patent_app_country] => US [patent_app_date] => 2024-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19137256 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/137256
MEMORY CAPACITY ADJUSTMENT METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM Aug 11, 2024 Pending
Array ( [id] => 19603163 [patent_doc_number] => 20240394043 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-28 [patent_title] => APPARATUS AND METHODS FOR AUTOMATICALLY REMOVING DATA OF MOBILE DEVICES [patent_app_type] => utility [patent_app_number] => 18/797618 [patent_app_country] => US [patent_app_date] => 2024-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6290 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18797618 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/797618
Apparatus and methods for automatically removing data of mobile devices Aug 7, 2024 Issued
Array ( [id] => 19725885 [patent_doc_number] => 20250028636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY [patent_app_type] => utility [patent_app_number] => 18/794937 [patent_app_country] => US [patent_app_date] => 2024-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18794937 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/794937
Interconnect based address mapping for improved reliability Aug 4, 2024 Issued
Menu