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Nathan Sadler

Examiner (ID: 7400)

Most Active Art Unit
2139
Art Unit(s)
2189, 2139
Total Applications
791
Issued Applications
554
Pending Applications
55
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19834323 [patent_doc_number] => 20250086109 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-13 [patent_title] => METHODS FOR MANAGING STORAGE OPERATIONS FOR MULTIPLE HOSTS COUPLED TO DUAL-PORT SOLID-STATE DISKS AND DEVICES THEREOF [patent_app_type] => utility [patent_app_number] => 18/790854 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10374 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790854 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/790854
METHODS FOR MANAGING STORAGE OPERATIONS FOR MULTIPLE HOSTS COUPLED TO DUAL-PORT SOLID-STATE DISKS AND DEVICES THEREOF Jul 30, 2024 Pending
Array ( [id] => 19992715 [patent_doc_number] => 20250130937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-24 [patent_title] => ADDRESS TRANSLATION IN A MEMORY SUB-SYSTEM FOR MEMORY POOLING [patent_app_type] => utility [patent_app_number] => 18/781982 [patent_app_country] => US [patent_app_date] => 2024-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7353 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18781982 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/781982
ADDRESS TRANSLATION IN A MEMORY SUB-SYSTEM FOR MEMORY POOLING Jul 22, 2024 Pending
Array ( [id] => 20052151 [patent_doc_number] => 20250190373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-12 [patent_title] => OBJECT-LEVEL METADATA LOCATOR [patent_app_type] => utility [patent_app_number] => 18/774806 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -61 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18774806 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/774806
OBJECT-LEVEL METADATA LOCATOR Jul 15, 2024 Pending
Array ( [id] => 20474964 [patent_doc_number] => 20260017185 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => READ DISTURB DETECTION IN A MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/771436 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6578 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771436 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771436
READ DISTURB DETECTION IN A MEMORY SYSTEM Jul 11, 2024 Issued
Array ( [id] => 20528911 [patent_doc_number] => 12547346 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Block caching with queue identifiers [patent_app_type] => utility [patent_app_number] => 18/770926 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5016 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 320 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770926 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/770926
Block caching with queue identifiers Jul 11, 2024 Issued
Array ( [id] => 20474973 [patent_doc_number] => 20260017194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => TECHNIQUES FOR COMPRESSION AND MANAGEMENT OF METADATA [patent_app_type] => utility [patent_app_number] => 18/771053 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 44302 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771053 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/771053
Techniques for compression and management of metadata Jul 11, 2024 Issued
Array ( [id] => 19711092 [patent_doc_number] => 20250021234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => REDUCING TIME TO PROGRAM DURING ASYNCHRONOUS POWER LOSS HANDLING FOR A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/768815 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9526 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768815 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768815
REDUCING TIME TO PROGRAM DURING ASYNCHRONOUS POWER LOSS HANDLING FOR A MEMORY SUB-SYSTEM Jul 9, 2024 Pending
Array ( [id] => 20474963 [patent_doc_number] => 20260017184 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => RESERVED MEMORY SPACE IN COMPUTATIONAL STORAGE DEVICES [patent_app_type] => utility [patent_app_number] => 18/767846 [patent_app_country] => US [patent_app_date] => 2024-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6931 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18767846 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/767846
RESERVED MEMORY SPACE IN COMPUTATIONAL STORAGE DEVICES Jul 8, 2024 Issued
Array ( [id] => 20249872 [patent_doc_number] => 20250298741 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => MEMORY SYSTEMS AND OPERATION METHODS THEREOF AND STORAGE DEVICES AND OPERATION METHODS THEREOF [patent_app_type] => utility [patent_app_number] => 18/766226 [patent_app_country] => US [patent_app_date] => 2024-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18766226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/766226
MEMORY SYSTEMS AND OPERATION METHODS THEREOF AND STORAGE DEVICES AND OPERATION METHODS THEREOF Jul 7, 2024 Issued
Array ( [id] => 20447055 [patent_doc_number] => 20260003777 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY APPLIANCE SHARING MEMORY BETWEEN MULTIPLE HOSTS [patent_app_type] => utility [patent_app_number] => 18/759701 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18759701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/759701
MEMORY APPLIANCE SHARING MEMORY BETWEEN MULTIPLE HOSTS Jun 27, 2024 Abandoned
Array ( [id] => 19514270 [patent_doc_number] => 20240345956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => TAG UPDATE BUS FOR UPDATED COHERENCE STATE [patent_app_type] => utility [patent_app_number] => 18/754499 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16085 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18754499 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/754499
TAG UPDATE BUS FOR UPDATED COHERENCE STATE Jun 25, 2024 Pending
Array ( [id] => 19514043 [patent_doc_number] => 20240345729 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => STORAGE DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/752798 [patent_app_country] => US [patent_app_date] => 2024-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10968 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18752798 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/752798
STORAGE DEVICE, ELECTRONIC DEVICE INCLUDING THE SAME, AND OPERATING METHOD THEREOF Jun 24, 2024 Pending
Array ( [id] => 20609995 [patent_doc_number] => 12585597 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-24 [patent_title] => Memory with write address delay circuit [patent_app_type] => utility [patent_app_number] => 18/747497 [patent_app_country] => US [patent_app_date] => 2024-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4620 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18747497 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/747497
Memory with write address delay circuit Jun 18, 2024 Issued
Array ( [id] => 20242670 [patent_doc_number] => 12422988 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-09-23 [patent_title] => Hardware revocation engine for temporal memory safety [patent_app_type] => utility [patent_app_number] => 18/741701 [patent_app_country] => US [patent_app_date] => 2024-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1951 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18741701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/741701
Hardware revocation engine for temporal memory safety Jun 11, 2024 Issued
Array ( [id] => 20666532 [patent_doc_number] => 12608307 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-04-21 [patent_title] => Data storage device and method for writing updates to a host memory buffer using assistance from a host [patent_app_type] => utility [patent_app_number] => 18/736977 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 1231 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736977 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/736977
Data storage device and method for writing updates to a host memory buffer using assistance from a host Jun 6, 2024 Issued
Array ( [id] => 20659195 [patent_doc_number] => 20260111238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-23 [patent_title] => MEMORY SLOT CONTROL METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 19/168015 [patent_app_country] => US [patent_app_date] => 2024-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3664 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19168015 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/168015
MEMORY SLOT CONTROL METHOD AND APPARATUS, ELECTRONIC DEVICE, AND STORAGE MEDIUM May 30, 2024 Pending
Array ( [id] => 20351591 [patent_doc_number] => 20250348443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-11-13 [patent_title] => DEVICE CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 18/677920 [patent_app_country] => US [patent_app_date] => 2024-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4815 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18677920 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/677920
DEVICE CONTROL METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT May 29, 2024 Pending
Array ( [id] => 20174779 [patent_doc_number] => 12393526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-08-19 [patent_title] => NAND page buffer based security operations [patent_app_type] => utility [patent_app_number] => 18/672394 [patent_app_country] => US [patent_app_date] => 2024-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7098 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18672394 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/672394
NAND page buffer based security operations May 22, 2024 Issued
Array ( [id] => 20528904 [patent_doc_number] => 12547339 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-10 [patent_title] => Memory with efficient storage of event log data [patent_app_type] => utility [patent_app_number] => 18/646668 [patent_app_country] => US [patent_app_date] => 2024-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1214 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18646668 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/646668
Memory with efficient storage of event log data Apr 24, 2024 Issued
Array ( [id] => 20323274 [patent_doc_number] => 20250335362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => SYSTEMS, METHODS, AND MEDIA FOR PROVIDING APPEND-ONLY CACHES [patent_app_type] => utility [patent_app_number] => 18/645047 [patent_app_country] => US [patent_app_date] => 2024-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1297 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18645047 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/645047
SYSTEMS, METHODS, AND MEDIA FOR PROVIDING APPEND-ONLY CACHES Apr 23, 2024 Abandoned
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