Search

Nathan Sadler

Examiner (ID: 7400)

Most Active Art Unit
2139
Art Unit(s)
2189, 2139
Total Applications
791
Issued Applications
554
Pending Applications
55
Abandoned Applications
201

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18181766 [patent_doc_number] => 20230042495 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-09 [patent_title] => COARSE AND HIERARCHICAL SWEEP SAMPLING IN MEMORY TRAINING [patent_app_type] => utility [patent_app_number] => 17/967037 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10683 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17967037 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/967037
COARSE AND HIERARCHICAL SWEEP SAMPLING IN MEMORY TRAINING Oct 16, 2022 Pending
Array ( [id] => 18306666 [patent_doc_number] => 20230110566 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => METHOD FOR SYNCHRONIZATION FOR IMPROVING CONCURRENT READ PERFORMANCE OF CRITICAL SECTION IN DISTRIBUTED SHARED MEMORY AND APPARATUS USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/938654 [patent_app_country] => US [patent_app_date] => 2022-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5774 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17938654 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/938654
METHOD FOR SYNCHRONIZATION FOR IMPROVING CONCURRENT READ PERFORMANCE OF CRITICAL SECTION IN DISTRIBUTED SHARED MEMORY AND APPARATUS USING THE SAME Oct 5, 2022 Abandoned
Array ( [id] => 19136895 [patent_doc_number] => 11971853 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Optimizing removable media library file removal [patent_app_type] => utility [patent_app_number] => 17/936972 [patent_app_country] => US [patent_app_date] => 2022-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 6132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17936972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/936972
Optimizing removable media library file removal Sep 29, 2022 Issued
Array ( [id] => 19313356 [patent_doc_number] => 12039170 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-07-16 [patent_title] => Hardware revocation engine for temporal memory safety [patent_app_type] => utility [patent_app_number] => 17/934355 [patent_app_country] => US [patent_app_date] => 2022-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17934355 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/934355
Hardware revocation engine for temporal memory safety Sep 21, 2022 Issued
Array ( [id] => 19905424 [patent_doc_number] => 12282429 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-22 [patent_title] => Systems and methods for adaptive hybrid hardware pre-fetch [patent_app_type] => utility [patent_app_number] => 17/944031 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7963 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944031 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944031
Systems and methods for adaptive hybrid hardware pre-fetch Sep 12, 2022 Issued
Array ( [id] => 18240245 [patent_doc_number] => 20230072556 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => PROCESSING UNIT ARCHITECTURES AND TECHNIQUES FOR REUSABLE INSTRUCTIONS AND DATA [patent_app_type] => utility [patent_app_number] => 17/944014 [patent_app_country] => US [patent_app_date] => 2022-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5981 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17944014 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/944014
PROCESSING UNIT ARCHITECTURES AND TECHNIQUES FOR REUSABLE INSTRUCTIONS AND DATA Sep 12, 2022 Pending
Array ( [id] => 19355920 [patent_doc_number] => 12056366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-06 [patent_title] => Storage system [patent_app_type] => utility [patent_app_number] => 17/940371 [patent_app_country] => US [patent_app_date] => 2022-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 19493 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17940371 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/940371
Storage system Sep 7, 2022 Issued
Array ( [id] => 18644702 [patent_doc_number] => 11768770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Cache memory addressing [patent_app_type] => utility [patent_app_number] => 17/823480 [patent_app_country] => US [patent_app_date] => 2022-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17823480 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/823480
Cache memory addressing Aug 29, 2022 Issued
Array ( [id] => 18254192 [patent_doc_number] => 20230081231 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => INTERCONNECT BASED ADDRESS MAPPING FOR IMPROVED RELIABILITY [patent_app_type] => utility [patent_app_number] => 17/893790 [patent_app_country] => US [patent_app_date] => 2022-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17893790 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/893790
Interconnect based address mapping for improved reliability Aug 22, 2022 Issued
Array ( [id] => 19780411 [patent_doc_number] => 12229444 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-18 [patent_title] => Command scheduling for a memory system [patent_app_type] => utility [patent_app_number] => 17/892960 [patent_app_country] => US [patent_app_date] => 2022-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 14678 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17892960 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/892960
Command scheduling for a memory system Aug 21, 2022 Issued
Array ( [id] => 18651664 [patent_doc_number] => 20230297500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => DATA STORAGE DEVICE FOR DETERMINING A WRITE ADDRESS USING A NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/889297 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4487 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889297
Data storage device for determining a write address using a neural network Aug 15, 2022 Issued
Array ( [id] => 18989606 [patent_doc_number] => 20240061575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-22 [patent_title] => OPEN BLOCK MANAGEMENT IN MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 17/889179 [patent_app_country] => US [patent_app_date] => 2022-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10952 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17889179 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/889179
Open block management in memory devices Aug 15, 2022 Issued
Array ( [id] => 18038263 [patent_doc_number] => 20220382479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM [patent_app_type] => utility [patent_app_number] => 17/819319 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17819319 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/819319
INFORMATION PROCESSING APPARATUS, INFORMATION PROCESSING METHOD, AND INFORMATION PROCESSING PROGRAM Aug 11, 2022 Abandoned
Array ( [id] => 18846841 [patent_doc_number] => 20230409245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => METHOD AND SYSTEM FOR SOLID STATE DRIVE (SSD)-BASED REDUNDANT ARRAY OF INDEPENDENT DISKS (RAID) [patent_app_type] => utility [patent_app_number] => 17/885756 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6739 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885756 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/885756
Method and system for solid state drive (SSD)-based redundant array of independent disks (RAID) Aug 10, 2022 Issued
Array ( [id] => 18973797 [patent_doc_number] => 20240053889 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => ENABLING OR DISABLING DATA REDUCTION BASED ON MEASURE OF DATA OVERWRITES [patent_app_type] => utility [patent_app_number] => 17/818805 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5995 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818805 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/818805
Enabling or disabling data reduction based on measure of data overwrites Aug 9, 2022 Issued
Array ( [id] => 18925502 [patent_doc_number] => 20240028506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-25 [patent_title] => MAPPING TABLE RE-BUILDING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT [patent_app_type] => utility [patent_app_number] => 17/882610 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6768 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882610 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882610
MAPPING TABLE RE-BUILDING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT Aug 7, 2022 Abandoned
Array ( [id] => 19137191 [patent_doc_number] => 11972154 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-30 [patent_title] => Configurable variable-length shift register circuits [patent_app_type] => utility [patent_app_number] => 17/816758 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 6 [patent_no_of_words] => 5545 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17816758 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/816758
Configurable variable-length shift register circuits Aug 1, 2022 Issued
Array ( [id] => 19538501 [patent_doc_number] => 12131054 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Storage device [patent_app_type] => utility [patent_app_number] => 17/877297 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 16024 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877297
Storage device Jul 28, 2022 Issued
Array ( [id] => 19078433 [patent_doc_number] => 11947801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-02 [patent_title] => In-place memory copy during remote data transfer in heterogeneous compute environment [patent_app_type] => utility [patent_app_number] => 17/876936 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 24681 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876936 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876936
In-place memory copy during remote data transfer in heterogeneous compute environment Jul 28, 2022 Issued
Array ( [id] => 19122353 [patent_doc_number] => 11966335 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-23 [patent_title] => Hardware interconnect with memory coherence [patent_app_type] => utility [patent_app_number] => 17/876110 [patent_app_country] => US [patent_app_date] => 2022-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10248 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17876110 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/876110
Hardware interconnect with memory coherence Jul 27, 2022 Issued
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